Semiconductor device and manufacturing method thereof

ABSTRACT

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

TECHNICAL FIELD

The present invention relates to a semiconductor device including atransistor.

Note that the semiconductor device in this specification refers to anydevice that can function by utilizing semiconductor characteristics, andsemiconductor elements and circuits, electro-optic devices includingsemiconductor elements and circuits, and electronic devices includingsemiconductor elements and circuits are all semiconductor devices.

BACKGROUND ART

In recent years, a technique by which transistors are formed usingsemiconductor thin films formed over a substrate having an insulatingsurface has been attracting attention. A transistor is used for asemiconductor device typified by a liquid crystal television. As asemiconductor thin film that can be applied to the transistors, asilicon-based semiconductor material is known, and an oxidesemiconductor attracts attention as another material.

A transistor is manufactured mainly using a semiconductor material suchas amorphous silicon or polycrystalline silicon. A transistor formedusing amorphous silicon has low field-effect mobility, but such atransistor can be formed over a glass substrate with a larger area. Onthe other hand, a transistor formed using crystalline silicon has highfield-effect mobility, but a crystallization step such as laserannealing is necessary and such a transistor is not always suitable fora larger glass substrate.

As a material of the oxide semiconductor, zinc oxide and a materialcontaining zinc oxide as its component are known. Further, thin filmtransistors formed using an amorphous oxide (oxide semiconductor) havingan electron carrier concentration of less than 10¹⁸/cm³ are disclosed(Patent Documents 1 to 3).

Moreover, there is a trend in an active matrix semiconductor devicetypified by a liquid crystal display device towards a larger screen,e.g., a 60-inch diagonal screen, and further, the development of anactive matrix semiconductor device is aimed even at a screen size of adiagonal of 120 inches or more. In addition, a trend in resolution of ascreen is toward higher definition, e.g., high-definition (HD) imagequality (1366×768) or full high-definition (FHD) image quality(1920×1080), and prompt development of a so-called 4K Digital Cinemadisplay device, which has a resolution of 3840×2048 or 4096×2160, isalso pushed.

As a display device has a higher definition, the number of pixels neededfor it is significantly increased. As a result, writing time for onepixel is shortened, and thus a transistor is required to have high speedoperation characteristics, large on current, and the like. In themeantime, a problem of energy depletion in recent years has causeddemand for a display device whose power consumption is suppressed.Therefore, a transistor is also required to have low off-state currentand suppressed unnecessary leakage current.

REFERENCE Patent Document [Patent Document 1] Japanese Published PatentApplication No. 2006-165527 [Patent Document 2] Japanese PublishedPatent Application No. 2006-165528 [Patent Document 3] JapanesePublished Patent Application No. 2006-165529 DISCLOSURE OF INVENTION

A transistor using an oxide semiconductor has higher field-effectmobility than a transistor using amorphous silicon. However, atransistor using an oxide semiconductor has lower field-effect mobilitythan a transistor using polycrystalline silicon, so that field-effectmobility of a transistor using an oxide semiconductor is required to befurther improved.

In addition, a difference from the stoichiometric composition in anoxide semiconductor arises in a formation process. For example,electrical conductivity of an oxide semiconductor is changed due toexcess and deficiency of oxygen. Further, hydrogen that enters the oxidesemiconductor thin film during the formation of the thin film forms anoxygen (O)-hydrogen (H) bond and serves as an electron donor, which is afactor of changing electric conductivity. Further, the O—H bond is abond having polarity; and thus, the O—H bond might cause variation incharacteristics of an active device such as a transistor formed using anoxide semiconductor.

Even when the electron carrier concentration is lower than 10¹⁸/cm³, theoxide semiconductor is substantially n-type, and the on/off ratio of thetransistors disclosed in the above patent documents is only 10³. Such alow on/off ratio of the transistor is due to large off-state current.

The present invention is made in view of the foregoing technicalbackground. Therefore, an object of the present invention is to providea semiconductor device in which transistors with differentcharacteristics, specifically, a transistor with excellent dynamiccharacteristics (on characteristics or frequency characteristics(referred to as f characteristics)) and a transistor having a reducedoff-state current, are provided over one substrate. Further, anotherobject is to provide a simple method for manufacturing the semiconductordevice.

In order to achieve the above-described object, in the invention, anoxide semiconductor layer which is intrinsic or substantially intrinsicand includes a crystalline region in a surface portion is focused. Asemiconductor from which an impurity which is to be an electron donor(donor) from an oxide semiconductor is removed and which has a largerenergy gap than a silicon semiconductor can be used as a semiconductorwhich is intrinsic or substantially intrinsic. The electriccharacteristics of transistors is controlled by controlling thepotential of a pair of conductive films which are provided on oppositesides form each other with respect to the oxide semiconductor layer,each with an insulating film arranged therebetween, so that the positionof a channel formed in the oxide semiconductor layer is determined.

One embodiment of the present invention is a semiconductor device inwhich a transistor with excellent dynamic characteristics and atransistor with stable electric characteristics (e.g., an extremelyreduced off-state current) are used over one substrate. Specifically, anembodiment of the present invention is a semiconductor from which animpurity which is to be an electron donor (donor) from an oxidesemiconductor is removed and which has a larger energy gap than asilicon semiconductor can be used. Using the oxide semiconductor, anoxide semiconductor layer which is intrinsic or substantially intrinsicand includes a crystalline region in a surface portion of the oxidesemiconductor layer is formed. In addition, a plurality of transistorshaving a structure in which conductive films which are provided onopposite sides from each other with respect to the oxide semiconductorlayer, each with an insulating film arranged therebetween is providedover one substrate.

That is, an embodiment of the present invention is a semiconductordevice including a first electrode layer, a first insulating film overthe first electrode layer, an oxide semiconductor layer including acrystalline region in a surface portion of the oxide semiconductorlayer, over the first insulating film, a second electrode layer and athird electrode layer over the first electrode layer and in contact withthe oxide semiconductor layer, the second electrode layer having an endportion overlapping with the first electrode layer, and the thirdelectrode layer having an end portion overlapping with the firstelectrode layer, a second insulating film including an oxide insulatingfilm in contact with the second electrode layer, the third electrodelayer, and the oxide semiconductor layer, and a fourth electrode layeroverlapping with the first electrode layer and the oxide semiconductorlayer, over the second insulating film. In addition, the semiconductordevice includes a plurality of transistors in which an energy gap of anoxide semiconductor used in the oxide semiconductor layer is greaterthan or equal to 2 eV.

An embodiment of the present invention is an inverter circuit whichincludes the above-described semiconductor device including a depressiontransistor and an enhancement transistor.

An embodiment of the present invention is includes a display devicewhich includes the above-described semiconductor device including apixel portion and a driver circuit portion which drives the pixelportion.

An embodiment of the present invention is a driving method using thefirst electrode layer as a main gate electrode in at least onetransistor and the fourth electrode layer as a main gate electrode inthe other transistors in the above-described semiconductor device.

An embodiment of the present invention is a driving method using thefourth electrode layer as a main gate electrode in the depletiontransistor and the fourth electrode layer as a main gate electrode inthe enhancement transistor in the above-described inverter circuit.

An embodiment of the present invention is a driving method using thefirst electrode layer as a main gate electrode in at least onetransistor included in the pixel portion and the fourth electrode layeras a main gate electrode in at least one transistor included in thedriver circuit portion in the above-described display device.

An embodiment of the present invention is a manufacturing method of asemiconductor device including the steps of forming a first electrodelayer, forming a first insulating film over the first electrode layer,forming an oxide semiconductor layer over the first insulating film,performing dehydration or dehydrogenation on the oxide semiconductorlayer so that a crystalline region is formed in a surface portion of theoxide semiconductor layer, forming a second electrode layer and a thirdelectrode layer over the first electrode layer and in contact with theoxide semiconductor layer, the second electrode layer having an endportion overlapping with the first electrode layer, and the thirdelectrode layer having an end portion overlapping with the firstelectrode layer, forming a second insulating film including an oxideinsulating film in contact with the second electrode layer, the thirdelectrode layer, and the oxide semiconductor layer, and forming a fourthelectrode layer overlapping with the first electrode layer and the oxidesemiconductor layer, over the second insulating film. In addition, theabove-described semiconductor device includes a plurality of transistorsover one substrate in which an energy gap of an oxide semiconductor usedin the oxide semiconductor layer is greater than or equal to 2 eV.

In this specification, an EL layer refers to a layer provided between apair of electrodes in a light-emitting element. Thus, a light-emittinglayer containing an organic compound that is a light-emitting substancewhich is interposed between electrodes is an embodiment of the EL layer.

Note that in this specification, a light-emitting device refers to animage display device, a light-emitting device, or a light source(including a lighting device). In addition, the light-emitting deviceincludes any of the following modules in its category: a module in whicha connector such as a flexible printed circuit (FPC), a tape automatedbonding (TAB) tape, or a tape carrier package (TCP) is attached to alight-emitting device; a module having a TAB tape or a TCP provided witha printed wiring board at the end thereof; and a module having anintegrated circuit (IC) directly mounted over a substrate over which alight-emitting element is formed by a chip on glass (COG) method.

According to one embodiment of the present invention, a crystallineregion included in an oxide semiconductor layer is used as a channelformation region, whereby operation speed of the circuit included in asemiconductor device can be increased. In addition, a circuit is formedusing a transistor in which a purified oxide semiconductor is used,whereby operation of the circuit included in a semiconductor device canbe stabilized. Further, off-state current reduced to 1×10⁻¹³ A or lower,whereby a storage capacitor included in a semiconductor device can bereduced in size or in number. Further, a semiconductor device includingtransistors with different characteristics over one substrate can beprovided. Furthermore, the semiconductor device can be manufactured by asimple method.

BRIEF DESCRIPTION OF DRAWINGS

In the accompanying drawings;

FIGS. 1A to 1E each illustrate a manufacturing method of a semiconductordevice according to an embodiment;

FIG. 2 illustrates a semiconductor device according to an embodiment;

FIGS. 3A to 3C each illustrate an inverter circuit according to anembodiment;

FIGS. 4A to 4C each illustrate a shift register according to anembodiment;

FIGS. 5A and 5B each illustrate a pulse output circuit according to anembodiment;

FIGS. 6A to 6D each illustrate a pulse output circuit according to anembodiment;

FIGS. 7A to 7D each illustrate a pulse output circuit according to anembodiment;

FIGS. 8A and 8B each illustrate a timing chart according to anembodiment;

FIGS. 9A and 9B are block diagrams of display devices according to anembodiment;

FIGS. 10A and 10B each illustrate a driver circuit of a display deviceaccording to an embodiment;

FIGS. 11A1 and 11A2 are cross-sectional views and FIG. 11B is a planview each illustrating an embodiment of the present invention;

FIG. 12 is a cross-sectional view illustrating an embodiment of thepresent invention;

FIG. 13 is a cross-sectional view illustrating an embodiment of thepresent invention;

FIG. 14 shows an equivalent circuit of a pixel in a semiconductordevice;

FIGS. 15A to 15C are cross-sectional views each illustrating anembodiment of the present invention;

FIGS. 16A and 16B are a cross-sectional view and a plan view,respectively, illustrating an embodiment of the present invention;

FIGS. 17A and 17B each illustrate an example of a usage mode ofelectronic paper;

FIG. 18 is an external view illustrating an example of an electronicbook reader;

FIGS. 19A and 19B are external views illustrating examples of atelevision device and a digital photo frame, respectively;

FIGS. 20A and 20B are external views illustrating examples of gamemachines;

FIGS. 21A and 21B are external views illustrating examples of cellularphones;

FIGS. 22A1, 22A2, 22B1 and 22B2 are each illustrates an end portion of adisplay device according to an embodiment;

FIG. 23 is a longitudinal cross-sectional view of an inverted staggeredtransistor in which an oxide semiconductor is used;

FIG. 24A shows energy band diagrams (schematic diagrams) along thesection A-A′ illustrated in FIG. 23 in the case in which the potentialof the source and the potential of the drain are the same (V_(D)=0), andFIG. 24B shows energy band diagrams (schematic diagrams) along A-A′illustrated in FIG. 23 in the case in which positive potential isapplied to the drain (V_(D)>0) with respect to the source;

FIG. 25 shows an energy band diagram (a schematic diagram) along thesection B-B′ illustrated in FIG. 23 in the case in which the gatevoltage is 0 V;

FIG. 26A shows an energy band diagram (a schematic diagram) along B-B′illustrated in FIG. 23 in the case in which a positive potential(V_(G)>0) is applied to a gate (GE1), and FIG. 26B shows an energy banddiagram (a schematic diagram) along B-B′ illustrated in FIG. 23 in thecase in which a negative potential (V_(G)<0) is applied to the gate(GE1); and

FIG. 27 shows a relation between the vacuum level and the work functionof a metal (ϕM), and between the vacuum level and the electron affinityof an oxide semiconductor (χ).

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. Note that thepresent invention is not limited to the description below and it iseasily understood by those skilled in the art that the mode and detailscan be changed variously. Therefore, the present invention is notconstrued as being limited to description of the embodiments. Note thatin the drawings of this specification, the identical portions orportions having a similar function are denoted by the identicalreference numerals, and description thereon may be omitted.

Embodiment 1

In this embodiment, one embodiment of a substrate provided with acircuit of a display device and a manufacturing method of the substrateprovided with a circuit as one embodiment of a semiconductor device anda manufacturing method of the semiconductor device will be describedwith reference to FIGS. 1A to 1E.

FIG. 1E illustrates an example of a cross-sectional structure of aplurality of transistors formed over a substrate provided with a circuitof a display device. Transistors 440A and 440B illustrated in FIG. 1Eeach have a kind of four-terminal structure in which a pair of electrodelayers which are provided on opposite sides from each other with respectto a channel formation region of an oxide semiconductor layer, each withan insulating film arranged therebetween. Note that a so-calleddual-gate transistor in which a pair of electrode layers which areprovided on opposite sides from each other with respect to a channelformation region of an oxide semiconductor layer, each with aninsulating film arranged therebetween is one embodiment of thefour-terminal structure of this embodiment. Further, the case where thetransistor 440B is applied to a pixel of a display device and thetransistor 440A is applied to part of a driver circuit arranged in theperiphery of a pixel portion will be described.

The transistor 440A includes a first electrode layer 421 a, a firstinsulating layer 402, an oxide semiconductor layer 404 a including acrystalline region 405 a, a second electrode layer 455 a, and a thirdelectrode layer 455 b over a substrate 400 having an insulating surface.In addition, the transistor 440A includes a second insulating layer 428which is in contact with the crystalline region 405 a and covers thetransistor 440A, and a fourth electrode layer 422 a which is providedover a channel formation region with the second insulating layer 428interposed therebetween. The first electrode layer 421 a and the oxidesemiconductor layer 404 a including the crystalline region 405 a overlapwith each other with the first insulating layer 402 interposedtherebetween. Further, the second electrode layer 455 a and the thirdelectrode layer 455 b are formed over the oxide semiconductor layer 404a so that part of the second electrode layer 455 a part of the thirdelectrode layer 455 b overlap with the oxide semiconductor layer 404 a.

The transistor 440B includes a first electrode layer 421 b, the firstinsulating layer 402, an oxide semiconductor layer 404 b including acrystalline region 405 b, a second electrode layer 455 c, and a thirdelectrode layer 455 d over the substrate 400 having an insulatingsurface. In addition, the transistor 440B includes the second insulatinglayer 428 which is in contact with the crystalline region 405 b andcovers the transistor 440B and a fourth electrode layer 422 b which isprovided over the channel formation region with the second insulatinglayer 428 interposed therebetween. The first electrode layer 421 b andthe oxide semiconductor layer 404 b including the crystalline region 405b overlap with each other with the first insulating layer 402 interposedtherebetween. Further, the second electrode layer 455 c and the thirdelectrode layer 455 d are formed over the oxide semiconductor layer 404b so that part of the second electrode layer 455 c part of the thirdelectrode layer 455 d overlap with the oxide semiconductor layer 404 b.

The transistors 440A and 440B each have a dual-gate structure. In atransistor having a dual-gate structure, one or both of electrode layerswhich are provided on opposite sides from each other with respect to anoxide semiconductor layer, each with an insulating film arrangedtherebetween can be used as a gate electrode layer. Note that the secondelectrode layer and the third electrode layer function as a sourceelectrode layer and a drain electrode layer.

In this embodiment, the fourth electrode layer 422 a of the transistor440A is used as a main gate electrode of the transistor. Accordingly, achannel is formed in a region which is positioned between a region incontact with the second electrode layer 455 a of the oxide semiconductorlayer 404 a and a region in contact with the third electrode layer 455 bof the oxide semiconductor layer 404 a, which is in contact with thesecond insulating layer 428, and which overlaps with the fourthelectrode layer 422 a.

The first electrode layer and the fourth electrode layer are provided onopposite sides from each other with respect to the oxide semiconductorlayer, each with the insulating film arranged therebetween. Note that inthis embodiment, in the case where the potential of the first electrodelayer is higher that that of the fourth electrode layer, the firstelectrode layer is referred to as a main gate electrode, and in the casewhere the potential of the fourth electrode layer is higher that that ofthe first electrode layer, the fourth electrode layer is referred to asa main gate electrode. The potential of either the first electrode layeror the fourth electrode layer may be GND, 0 V, or in a floating state.

The first electrode layer 421 b of the transistor 440B is used as a maingate electrode of the transistor. Accordingly, a channel is formed in aregion which is positioned between a region in contact with the secondelectrode layer 455 c of the oxide semiconductor layer 404 b and aregion in contact with the third electrode layer 455 d of the oxidesemiconductor layer 404 b, which is in contact with the first insulatinglayer 402, and which overlaps with the first electrode layer 421 b.

Note that the transistor 440B can have a light-transmitting propertywhen the first electrode layer 421 b, the second electrode layer 455 c,the third electrode layer 455 b, and the fourth electrode layer 422 bare formed using a light-transmitting conductive film. In the case wherea light-transmitting transistor is applied to a pixel of a displaydevice, the aperture ratio of the pixel can be improved.

As a material of the light-transmitting conductive film, a conductivematerial that transmits visible light, for example, an In—Sn—O-basedoxide conductive material, an In—Sn—Zn—O-based oxide conductivematerial, an In—Al—Zn—O-based oxide conductive material, anSn—Ga—Zn—O-based oxide conductive material, an Al—Ga—Zn—O-based oxideconductive material, an Sn—Al—Zn—O-based oxide conductive material, anIn—Zn—O-based oxide conductive material, an Sn—Zn—O-based oxideconductive material, an Al—Zn—O-based oxide conductive material, anIn—O-based oxide conductive material, an Sn—O-based oxide conductivematerial, or a Zn—O-based oxide conductive material can be employed. Inthe case of using a sputtering method, deposition may be performed witha target including SiO₂ at greater than or equal to 2 wt % and less thanor equal to 10 wt % so that the light-transmitting conductive film mayinclude SiO_(x) (X>0) and be amorphous.

The first electrode layer 421 a, the second electrode layer 455 a, thethird electrode layer 455 b, and the fourth electrode layer 422 a of thetransistor 440A may be formed using a single-layer structure or astacked structure including a film containing an element selected fromTi, Mo, W, Al, Cr, Cu, and Ta as a main component. For the secondelectrode layer 455 a and the third electrode layer 455 b which areelectrically connected to the oxide semiconductor layer, a materialincluding metal with high oxygen affinity is preferably used.

As the oxide semiconductor layer, an In—Sn—Ga—Zn—O-based oxidesemiconductor layer which is a four-component metal oxide; anIn—Ga—Zn—O-based oxide semiconductor layer, an In—Sn—Zn—O-based oxidesemiconductor layer, an In—Al—Zn—O-based oxide semiconductor layer, aSn—Ga—Zn—O-based oxide semiconductor layer, an Al—Ga—Zn—O-based oxidesemiconductor layer, or a Sn—Al—Zn—O-based oxide semiconductor layerwhich are three-component metal oxides; an In—Zn—O-based oxidesemiconductor layer, a Sn—Zn—O-based oxide semiconductor layer, anAl—Zn—O-based oxide semiconductor layer, a Zn—Mg—O-based oxidesemiconductor layer, a Sn—Mg—O-based oxide semiconductor layer, or anIn—Mg—O-based oxide semiconductor layer which are two-component metaloxides; or an In—O-based oxide semiconductor layer, a Sn—O-based oxidesemiconductor layer, or a Zn—O-based oxide semiconductor layer which areone-component metal oxides can be used. Further, SiO₂ may be containedin the above oxide semiconductor layer.

As the oxide semiconductor layer, a thin film represented byInMO₃(ZnO)_(m) (m>0) can be used. Here, M represents one or more metalelements selected from Ga, Al, Mn, and Co. For example, M may be Ga, Gaand Al, Ga and Mn, Ga and Co, or the like. An oxide semiconductor layerwhose composition formula is represented by InMO₃ (ZnO)_(m) (m>0), whichincludes Ga as M, is referred to as an In—Ga—Zn—O-based oxidesemiconductor described above, and a thin film of the In-Ga—Zn-O oxidesemiconductor is also referred to as an In—Ga—Zn—O-based film.

For the oxide semiconductor layer, the one which is subjected todehydration or dehydrogenation at high temperature in a short time by arapid thermal annealing (RTA) method or the like is used. This heatingprocess makes a superficial portion of the oxide semiconductor layerhave a crystalline region including so-called nanocrystals with a grainsize of greater than or equal to 1 nm and less than or equal to 20 nmand the rest of the oxide semiconductor layer is amorphous or is formedof a mixture of amorphousness and microcrystals, where an amorphousregion is dotted with microcrystals. Note that the above-described sizeof the nanocrystal is just an example, and the present invention is notconstrued as being limited to the above range.

In an oxide semiconductor layer having such a structure, a densecrystalline region including nanocrystals exists in its superficialportion. Therefore, in the case of using such an oxide semiconductorlayer, a change to an n-type, which is attributed to entry of moistureto the superficial portion or elimination of oxygen from the superficialportion, can be prevented. As a result, deterioration of electriccharacteristics influenced by a change to an n-type, specificallyincrease in the off-state current can be prevented.

The crystalline region in the superficial portion of the oxidesemiconductor layer includes crystal grains in which c-axes are orientedin a direction substantially perpendicular to a surface of the oxidesemiconductor layer. For example, in the case of using anIn—Ga—Zn—O-based oxide semiconductor material, the c-axes of the crystalgrains of In₂Ga₂ZnO₇ in the crystalline region are oriented in adirection substantially perpendicular to the surface of the oxidesemiconductor layer. The crystalline region includes nanocrystals whichare oriented in a predetermined direction. For example, in the casewhere an In—Ga—Zn—O-based oxide semiconductor material is used for theoxide semiconductor layer and nanocrystals are arranged so that c-axesof In₂Ga₂ZnO₇ are oriented in a direction substantially perpendicular toa substrate plane (or the surface of the oxide semiconductor layer),current flows in a b-axis direction (or an a-axis direction) ofIn₂Ga₂ZnO₇ in the transistor.

Note that the crystalline region may include a portion other than thecrystal grains. The crystal structure of the crystal grains is notlimited to the above structure, and the crystalline region may includecrystal grains of another structure. For example, in the case of usingan In—Ga—Zn—O-based oxide semiconductor material, crystal grains ofInGaZnO₄ may be included in addition to the crystal grains ofIn₂Ga₂ZnO₇.

Hereinafter, a manufacturing process of the transistor 440A and thetransistor 440B over one substrate is described with reference to FIGS.1A to 1E.

First, a conductive film is formed over the substrate 400 having aninsulating surface and a first photolithography step is performedthereon to form the first electrode layer 421 a and the first electrodelayer 421 b. At this time, etching is preferably performed so that atleast an end portion of the first electrode layer 421 a and the firstelectrode layer 421 b be tapered in order to prevent disconnection.

Note that a resist mask may be formed by an inkjet method. Formation ofthe resist mask by an inkjet method needs no photomask; thus,manufacturing cost can be reduced. Needless to say, an inkjet method canbe applied not only to the first photolithography step but also toanother photolithography step.

Note that as the substrate 400, any of the following substrates can beused: non-alkaline glass substrates formed using barium borosilicateglass, aluminoborosilicate glass, aluminosilicate glass, and the like bya fusion method or a float method; ceramic substrates; plasticsubstrates having heat resistance enough to withstand a processtemperature of this manufacturing process; and the like. Alternatively,a metal substrate such as a stainless steel alloy substrate which isprovided with an insulating film over the surface may also be used.

Note that as the above glass substrate, a substrate formed of aninsulator such as a ceramic substrate, a quartz substrate, or a sapphiresubstrate may be used. Alternatively, a crystallized glass substrate orthe like may be used.

The first electrode layer 421 a and the first electrode layer 421 b canbe formed using a single layer or a stacked layer using any of thefollowing: a metal material such as aluminum, copper, molybdenum,titanium, chromium, tantalum, tungsten, neodymium, or scandium; an alloymaterial which contains any of these materials as a main component; anda nitride containing any of these materials. Preferably, it is effectiveto form the first electrode layers with the use of a low-resistancemetal material such as aluminum or copper, the low-resistance metalmaterial is preferably used in combination with a refractory metalmaterial because it has disadvantages such as low heat resistance and atendency to be corroded. As the refractory metal material, molybdenum,titanium, chromium, tantalum, tungsten, neodymium, scandium, or the likecan be used.

At that time, a light-transmitting oxide conductive layer is used forpart of the electrode layer and the wiring layer to increase theaperture ratio. For example, an oxide conductive layer including indiumoxide, an alloy of indium oxide and tin oxide, an alloy of indium oxideand zinc oxide, zinc oxide, zinc aluminum oxide, zinc aluminumoxynitride, zinc gallium oxide, or the like can be used for thelight-transmitting conductive layer.

Further, the first electrode layer 421 a and the first electrode layer421 b may be formed using different materials. For example, in order toimprove the aperture ratio of a pixel portion, the first electrode layer421 b can be formed using a light-transmitting conductive layer withrespect to visible light, and in order to suppress wiring resistance,the first electrode layer 421 a in a driver circuit portion can beformed using a conductive film including metal as its main component,for example, a single film containing an element selected from titanium,molybdenum, tungsten, aluminum, chromium, copper, and tantalum as a maincomponent or a stacked layer film including the film.

An insulating layer serving as a base film may be provided between thesubstrate 400 and the first electrode layers 421 a and 421 b. The basefilm has a function of preventing diffusion of an impurity element fromthe substrate 400, and can be formed to have a single-layer orstacked-layer structure including one or more of a silicon nitride film,a silicon oxide film, a silicon nitride oxide film, and a siliconoxynitride film.

Next, the first insulating layer 402 is formed over the first electrodelayer 421 a and the first electrode layer 421 b. As the first insulatinglayer 402, a single-layer film or a stacked-layer film of any of siliconoxide layer, silicon oxynitride layer, silicon nitride oxide layer,silicon nitride layer, aluminum oxide layer, tantalum oxide layer, andthe like can be used. The first insulating layer 402 is formed to athickness greater than or equal to 50 nm and less than or equal to 250nm with a CVD method, a sputtering method, or the like. Note that in thefirst insulating layer 402, an oxide insulating layer is providedpreferably on the side where the first insulating layer 402 is incontact with the oxide semiconductor layer.

Note that the oxide semiconductor which becomes i-type or becomessubstantially i-type (an oxide semiconductor which is purified) due toremoval of an impurity is extremely sensitive to an interface statedensity or an interface electric charge; therefore, an interface withthe insulating film is important. Accordingly, the insulating film whichis in contact with the oxide semiconductor with high purity needs to beof high quality.

For example, high-density plasma CVD using microwaves (2.45 GHz) ispreferable in that it produces a dense high-quality insulating film withhigh dielectric withstand voltage. This is because a close contactbetween an oxide semiconductor with high purity and a high-quality gateinsulating film reduces interface state density and produces favorableinterface characteristics.

In addition, since the insulating film formed using the high-densityplasma CVD apparatus can have a uniform thickness, the insulating filmhas excellent step coverage. Further, the thickness of a thin insulatingfilm formed with the high-density plasma CVD apparatus can be controlledprecisely.

Needless to say, another method such as sputtering method or plasma CVDmethod can be employed as long as the method enables formation of agood-quality insulating film as a gate insulating film. Alternatively,an insulating film whose film quality and interface characteristics withthe oxide semiconductor are improved by heat treatment performed afterformation of the insulating film may be used. In any case, anyinsulating film that has a reduced interface state density with theoxide semiconductor and can form a favorable interface as well as havinga favorable film quality as a gate insulating film can be used.

The first insulating layer 402 is formed using a high-density plasma CVDapparatus. Here, a high-density plasma CVD apparatus refers to anapparatus which can realize a plasma density higher than or equal to1×10¹¹/cm³. For example, plasma is generated by applying a microwavepower higher than or equal to 3 kW and lower than or equal to 6 kW sothat the insulating film is formed.

A monosilane gas (SiH₄), nitrous oxide (N₂O), and a rare gas areintroduced into a chamber as a source gas to generate high-densityplasma at a pressure higher than or equal to 10 Pa and lower than orequal to 30 Pa so that an insulating film is formed over a substratehaving an insulating surface, such as a glass substrate. After that, thesupply of a monosilane gas may be stopped, and nitrous oxide (N₂O) and arare gas may be introduced without exposure to the air to perform plasmatreatment performed on a surface of the insulating film. The plasmatreatment performed on the surface of the insulating film by introducingnitrous oxide (N₂O) and a rare gas is performed at least after theinsulating film is formed. The insulating film formed through the aboveprocess procedure has a small thickness and is an insulating film whosereliability can be ensured even though it has a thickness less than 100nm, for example.

In forming the first insulating layer 402, the flow ratio of amonosilane gas (SiH₄) to nitrous oxide (N₂O) which are introduced intothe chamber is in the range of 1:10 to 1:200. In addition, as a rare gaswhich is introduced into the chamber, helium, argon, krypton, xenon, orthe like can be used. In particular, argon, which is inexpensive, ispreferably used.

In addition, since the insulating film formed by using the high-densityplasma apparatus can have a uniform thickness, the insulating film hasexcellent step coverage. Further, with the high-density plasmaapparatus, the thickness of a thin insulating film can be controlledprecisely.

The insulating film formed through the above process procedure isgreatly different from the insulating film formed using a conventionalparallel plate PCVD apparatus. The etching rate of the insulating filmformed through the above process procedure is lower than that of theinsulating film formed using the conventional parallel plate PCVDapparatus by greater than or equal to 10% or greater than or equal to20% in the case where the etching rates with the same etchant arecompared to each other. Thus, it can be said that the insulating filmformed using the high-density plasma apparatus is a dense film.

Alternatively, a silicon oxide layer formed by a CVD method using anorganosilane gas can be used for the first insulating layer 402. As anorganosilane gas, a silicon-containing compound such astetraethoxysilane (TEOS) (chemical formula: Si(OC₂H₅)₄),tetramethylsilane (TMS) (chemical formula: Si(CH₃)₄),tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane(OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (chemical formula:SiH(OC₂H₅)₃), or trisdimethylaminosilane (chemical formula:SiH(N(CH₃)₂)₃) can be used.

Alternatively, the first insulating layer 402 may be formed using onekind of oxide, nitride, oxynitride, and nitride oxide of aluminum,yttrium, or hafnium; or a compound including at least two or more kindsof the above.

Note that in this specification, oxynitride refers to a substance thatcontains more oxygen atoms than nitrogen atoms and nitride oxide refersto a substance that contains more nitrogen atoms than oxygen atoms. Forexample, a “silicon oxynitride film” means a film that contains oxygenatoms and nitrogen atoms so that the number of the oxygen atoms islarger than that of the nitrogen atoms and, in the case wheremeasurements are performed using Rutherford backscattering spectrometry(RBS) and hydrogen forward scattering (HFS), contains oxygen, nitrogen,silicon, and hydrogen at concentrations ranging from 50 atomic % to 70atomic %, 0.5 atomic % to 15 atomic %, 25 atomic % to 35 atomic %, and0.1 atomic % to 10 atomic %, respectively. Further, a “silicon nitrideoxide film” means a film that contains nitrogen atoms and oxygen atomsso that the number of the nitrogen atoms is larger than that of theoxygen atoms and, in the case where measurements are performed using RBSand HFS, contains oxygen, nitrogen, silicon, and hydrogen atconcentrations ranging from 5 atomic % to 30 atomic %, 20 atomic % to 55atomic %, 25 atomic % to 35 atomic %, and 10 atomic % to 30 atomic %,respectively. Note that percentages of nitrogen, oxygen, silicon, andhydrogen fall within the ranges given above when the total number ofatoms contained in the silicon oxynitride film or the silicon nitrideoxide film is defined as 100 atomic %.

Next, over the first insulating layer 402, an oxide semiconductor film403 is formed to a thickness greater than or equal to 5 nm and less thanor equal to 200 nm, preferably greater than or equal to 10 nm and lessthan or equal to 20 nm (see FIG. 1A).

Note that before the oxide semiconductor film 403 is formed, dust on asurface of the first insulating layer 402 is preferably removed byreverse sputtering in which an argon gas is introduced and plasma isgenerated. The reverse sputtering refers to a method in which, withoutapplication of voltage to a target side, an RF power source is used forapplication of voltage to a substrate side in an argon atmosphere togenerate plasma in the vicinity of the substrate to modify a surface.Note that instead of an argon atmosphere, a nitrogen atmosphere, ahelium atmosphere, or the like may be used. Alternatively, an argonatmosphere to which oxygen, N₂O, or the like is added may be used.Further alternatively, an argon atmosphere to which Cl₂, CF₄, or thelike is added may be used. After the reverse sputtering, the oxidesemiconductor film is formed without being exposed to air, whereby dustor moisture can be prevented from attaching to an interface between thefirst insulating layer 402 and the oxide semiconductor film 403.

As the oxide semiconductor film, an In—Sn—Ga—Zn—O-based oxidesemiconductor layer which is a four-component metal oxide describedabove; an In—Ga—Zn—O-based oxide semiconductor layer, anIn—Sn—Zn—O-based oxide semiconductor layer, an In—Al—Zn—O-based oxidesemiconductor layer, a Sn—Ga—Zn—O-based oxide semiconductor layer, anAl—Ga—Zn—O-based oxide semiconductor layer, or a Sn—Al—Zn—O-based oxidesemiconductor layer which are three-component metal oxides describedabove; an In—Zn—O-based oxide semiconductor layer, a Sn—Zn—O-based oxidesemiconductor layer, an Al—Zn—O-based oxide semiconductor layer, aZn—Mg—O-based oxide semiconductor layer, a Sn—Mg—O-based oxidesemiconductor layer, or an In—Mg—O-based oxide semiconductor layer whichare two-component metal oxides described above; or an In—O-based oxidesemiconductor layer, a Sn—O-based oxide semiconductor layer, or aZn—O-based oxide semiconductor layer which are one-component metaloxides described above can be used. Further, SiO₂ may be contained inthe above oxide semiconductor film. As an oxide semiconductor film, anabove-described thin film expressed by InMO₃(ZnO)_(m) (m>0) can be used.

The oxide semiconductor film can be formed with a sputtering method in arare gas (typically argon) atmosphere, an oxygen atmosphere, or anatmosphere of a rare gas (typically argon) and oxygen. In the case ofusing a sputtering method, film deposition may be performed using atarget containing SiO₂ at greater than or equal to 2 percent by weightand less than or equal to 10 percent by weight and SiOx (x>0) whichinhibits crystallization may be contained in the oxide semiconductorfilm.

Here, film formation is performed using a target for forming an oxidesemiconductor including In, Ga, and Zn (the composition ratio ofIn₂O₃:Ga₂O₃:ZnO=1:1:1 [mol ratio] or In₂O₃:Ga₂O₃:ZnO=1:1:2 [mol ratio])under the following conditions: the distance between a substrate and atarget is 100 mm, the pressure is 0.6 Pa, the direct-current (DC) powersupply is 0.5 kW, and the atmosphere is oxygen (the flow rate of oxygenis 100%). Note that a pulse direct current (DC) power source ispreferable because powder substances (also referred to as particles ordust) generated in film formation can be reduced and the film thicknessdistribution can be uniform. In this embodiment, as the oxidesemiconductor film, an In—Ga—Zn—O-based film having a thickness of 15 nmis formed with a sputtering method using a target for forming anIn—Ga—Zn—O-based oxide semiconductor.

In that case, the oxide semiconductor film is preferably formed whilemoisture remaining in the treatment chamber is removed. This is forpreventing hydrogen, a hydroxyl group, or moisture from being containedin the oxide semiconductor film.

In addition, it is preferable that the oxide semiconductor film besuccessively formed over the first insulating layer 402. Themulti-chamber sputtering apparatus used here is provided with the targetof silicon or silicon oxide (artificial quarts), and the target forformation of an oxide semiconductor film. The deposition chamberprovided with the target for formation of an oxide semiconductor film isalso provided with at least a cryopump as an evacuation unit. Note thata turbo molecular pump may be used instead of the cryopump, and a coldtrap may be provided above an inlet of the turbo molecular pump so thatmoisture or the like may be adsorbed.

From the deposition chamber which is evacuated with the cryopump, ahydrogen atom, a compound containing a hydrogen atom such as H₂O, acarbon atom, a compound containing a carbon atom, and the like areremoved, whereby the concentration of an impurity in the oxidesemiconductor film formed in the deposition chamber can be reduced.

It is preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is reduced toapproximately the ppm level or the ppb level be used as the sputteringgas for the deposition of the oxide semiconductor film.

The oxide semiconductor film may be formed in the state where thesubstrate is heated. At that time, the substrate is heated higher thanor equal to 100° C. and lower than or equal to 600° C., preferably,higher than or equal to 200° C. and lower than or equal to 400° C. Byheating the substrate during deposition, the impurity concentration inthe oxide semiconductor film can be reduced.

Examples of a sputtering method include an RF sputtering method in whicha high-frequency power source is used as a sputtering power source, a DCsputtering method in which a direct-current power source is used, and apulsed DC sputtering method in which a bias is applied in a pulsedmanner. An RF sputtering method is mainly used in the case of forming aninsulating film, and a DC sputtering method is mainly used in the caseof forming a metal conductive film.

In addition, there is also a multi-source sputtering apparatus in whicha plurality of targets of different materials can be set. With themulti-source sputtering apparatus, films of different materials can beformed to be stacked in the same chamber, or a film of plural kinds ofmaterials can be formed by electric discharge at the same time in thesame chamber.

In addition, there are a sputtering apparatus provided with a magnetsystem inside the chamber and used for magnetron sputtering, and asputtering apparatus used for ECR sputtering in which plasma generatedwith the use of microwaves is used without using glow discharge.

Furthermore, as a deposition method by sputtering, there are also areactive sputtering method in which a target substance and a sputteringgas component are chemically reacted with each other during depositionto form a thin compound film thereof, and a bias sputtering method inwhich a voltage is also applied to a substrate during deposition.

Next, through a second photolithography step, a resist mask is formed.Then, the In—Ga—Zn—O-based film is etched. In etching, organic acid suchas citric acid or oxalic acid can be used for etchant. Etching isperformed so that the end portions of the oxide semiconductor layers 404a and 404 b have tapered shapes, breakage of a wiring due to a stepshape can be prevented. Note that etching here is not limited to wetetching and dry etching may also be used.

Next, dehydration or dehydrogenation of the oxide semiconductor layers404 a and 404 b is performed. First heat treatment for the dehydrationor dehydrogenation can be performed with the use of resistance heatingmethod, lamp irradiation, or the like in an inert gas atmosphere throughrapid thermal annealing (RTA) treatment at a temperature higher than orequal to 500° C. and lower than or equal to 750° C. (or a temperaturelower than or equal to the strain point of a glass substrate) forapproximately one minute to ten minutes, preferably at 650° C. forapproximately greater than or equal to three minutes and less than orequal to six minutes. With an RTA method, dehydration or dehydrogenationcan be performed in a short time; therefore, treatment can be performedeven at a temperature higher than the strain point of a glass substrate.Note that the timing of heat treatment is not limited to this timing andmay be performed plural times, for example, before and after aphotolithography step or a deposition step.

Note that in this specification, heat treatment in the atmosphere of aninert gas such as nitrogen or a rare gas is referred to as heattreatment for dehydration or dehydrogenation. In this specification,dehydrogenation does not refer to only elimination in the form of H₂ bythe heat treatment, and dehydration or dehydrogenation also refers toelimination of H, OH, and the like for convenience.

It is important that the temperature is decreased from the heatingtemperature T at which the oxide semiconductor layer is dehydrated ordehydrogenated to room temperature in the same furnace used for thedehydration or dehydrogenation with the oxide semiconductor layerprevented from being exposed to air so that entry of water or hydrogeninto the oxide semiconductor layer is prevented. When a transistor isformed using an i-type oxide semiconductor layer which is obtained bychanging an oxide semiconductor layer into a low-resistance oxidesemiconductor layer in an oxygen-deficient state, i.e., an n-type (e.g.,n⁻-type or n⁺-type) oxide semiconductor layer through dehydration ordehydrogenation and by changing the low-resistance oxide semiconductorlayer into a high-resistance oxide semiconductor layer through supply ofoxygen, the threshold voltage of the transistor can be positive, so thata switching element having so-called normally-off characteristics can berealized. It is preferable that a channel in a transistor of a displaydevice be formed at a positive threshold voltage which is as close to 0V as possible. If the threshold voltage of the transistor is negative,it tends to be normally on; in other words, current flows between thesource electrode and the drain electrode even when the gate voltage is 0V. In an active matrix display device, electric characteristics of atransistor included in a circuit are important and the performance ofthe display device depends on the electrical characteristics. Inparticular, of the electric characteristics of the transistor, thethreshold voltage (V_(th)) is important. When the threshold voltagevalue is high or is on the minus side even when the field effectmobility is high, it is difficult to control the circuit. In the casewhere a transistor has high threshold voltage, the transistor cannotperform a switching function as a transistor and might be a load when atransistor is driven at low voltage. In the case of an n-channeltransistor, it is desirable that only after a positive voltage isapplied as a gate voltage, a channel be formed and a drain currentflows. A transistor in which a channel is not formed unless drivingvoltage is raised and a transistor in which a channel is formed anddrain current flows even when negative voltage is applied are unsuitablefor a transistor used in a circuit.

In addition, when the temperature is decreased from the heatingtemperature T, the gas atmosphere may be switched to a gas atmospherewhich is different from that used when the temperature is raised to theheating temperature T. For example, cooling is performed by using thesame furnace that is used for the dehydration or dehydrogenation and byfilling the furnace with a high-purity oxygen gas, a high-purity N₂Ogas, or ultra-dry air (having a dew point of −40° C. or lower,preferably −60° C. or lower) without exposure to the air.

Note that in the first heat treatment, it is preferable that water,hydrogen, and the like be not contained in the atmosphere.Alternatively, the purity of an inert gas which is introduced into aheat treatment apparatus is preferably 6N (99.9999%) or more, morepreferably 7N (99.99999%) or more (that is, the impurity concentrationis 1 ppm or less, preferably 0.1 ppm or less).

In the case where heat treatment is performed under an inert gasatmosphere, an oxide semiconductor layer is changed into anoxygen-deficient oxide semiconductor layer by the heat treatment to be alow-resistant oxide semiconductor layer, i.e. an n-type (e.g., n⁻-type)oxide semiconductor layer. After that, oxygen is supplied to anoxygen-deficient portion of the oxide semiconductor layer by theformation of an oxide insulating layer which is in contact with theoxide semiconductor layer. Thus, the oxide semiconductor layer is madeto be i-type; that is, the oxide semiconductor layer is changed into ahigh-resistance oxide semiconductor layer. Accordingly, it is possibleto form a highly reliable transistor having favorable electriccharacteristics.

In the oxide semiconductor layer which is sufficiently dehydrated ordehydrogenated under the above conditions, at least a peak at aroundhigher than or equal to 250° C. and lower than or equal to 300° C. oftwo peaks in spectra which show discharge of moisture is not detectedwith thermal desorption spectroscopy (TDS) even when the temperature ofthe dehydrated or dehydrogenated oxide semiconductor layer is increasedto 450° C.

Note that the oxide semiconductor layer 404 a and the oxidesemiconductor layer 404 b are each an amorphous layer having manydangling bonds at the stage where the oxide semiconductor layers 404 aand 404 b are in an as-depo state. Through a first heating step for thedehydration or dehydrogenation, dangling bonds that exist close to eachother are bonded, so that the oxide semiconductor layers 404 a and 404 bcan have an ordered amorphous structure. When the ordering proceeds, theoxide semiconductor layers 404 a and 404 b are formed of a mixture ofamorphousness and microcrystals, where an amorphous region is dottedwith microcrystals, or are formed of amorphousness. The crystallineregion 405 a and the crystalline region 405 b including nanocrystals areformed in the superficial portion of the oxide semiconductor layer 404 aand the oxide semiconductor layer 404 b (FIG. 1B). The rest of the oxidesemiconductor layer 404 a and the oxide semiconductor layer 404 b cometo be amorphous or be formed of a mixture of amorphousness andmicrocrystals, where an amorphous region is dotted with microcrystals.Note that the crystalline region 405 a and the crystalline region 405 bare part of the oxide semiconductor layer 404 a and the oxidesemiconductor layer 404 b respectively, and hereinafter, the “the oxidesemiconductor layer 404 a” and “the oxide semiconductor layer 404 b”includes the crystalline region 405 a and the crystalline region 405 b,respectively. Here, the microcrystal is a so-called nanocrystal with aparticle size greater than or equal to 1 nm and less than or equal to 20nm, which is smaller than that of a microcrystalline particle generallycalled a microcrystal.

In the crystalline regions 405 a and 405 b, a nanocrystal which isc-axis-oriented in a direction perpendicular to a surface of the layeris preferably formed. In that case, it is preferable that the long axisof the crystal is in the c-axis direction and the size in the short-axisdirection is greater or equal to 1 nm and less or equal to 20 nm.

Note that, the crystalline region is not formed in a side surfaceportion of the oxide semiconductor layer depending on the order ofsteps, and in such a case, the crystalline region is formed only in asuperficial portion, except for the side surface portion. However, thearea of the side surface portion is small, and the effect of suppressingthe deterioration of electric characteristics or improving thedielectric withstand voltage can be maintained in that case as well.

Further, the first electrode layer 421 a and the first electrode layer421 b are crystallized to be microcrystalline layers or polycrystallinelayers in some cases, depending on the condition of the first heattreatment or a material of the first electrode layers 421 a and 421 b.For example, in the case where an indium tin oxide is used for amaterial of the first electrode layers 421 a and 421 b, they arecrystallized by the first heat treatment at 450° C. for one hour,whereas in the case where an indium tin oxide containing a silicon oxideis used as the first electrode layers 421 a and 421 b, they are noteasily crystallized.

The oxide semiconductor layers 404 a and 404 b after the first heattreatment are oxygen-deficient oxide semiconductor layers, and thecarrier concentration is higher than the carrier concentration rightafter the deposition and preferably 1×10¹⁸/cm³ or more. Thus the oxidesemiconductor layers 404 a and 404 b have lower resistance.

The first heat treatment for the oxide semiconductor layers can beperformed before the oxide semiconductor film is processed into theisland-shaped oxide semiconductor layers. In that case, after the firstheat treatment, the substrate is taken out of the heating apparatus andsubjected to a photolithography step to form the island-shaped oxidesemiconductor layers.

Then, although not illustrated, an opening (also referred to as acontact hole) for connecting the first electrode layer to the sourceelectrode layer or the drain electrode layer which will be describedlater is formed in the first insulating layer 402. The contact hole isformed by forming a mask over the first insulating layer 402 by aphotolithography method, an inkjet method, or the like, and thenselectively etching the first insulating layer 402 using the mask. Notethat the contact hole may be formed after the formation of the firstinsulating layer 402 and before the formation of the oxide semiconductorfilm 403.

Next, a conductive film which to be as a source electrode and a drainelectrode (including wires formed in the same layer as the sourceelectrode and the drain electrode) is formed over the oxidesemiconductor layers 404 a and 404 b. The conductive film is formed witha thickness greater than or equal to 100 and less than or equal to 500nm, preferably greater than or equal to 200 and less than or equal to300 nm.

The source electrode and the drain electrode are formed using a metalmaterial such as Al, Cu, Cr, Ta, Ti, Mo, or W, or an alloy materialcontaining any of these metal materials as its component. A structuremay be employed in which a high-melting-point metal layer of Cr, Ta, Ti,Mo, W, or the like is stacked over one side or both sides of a metallayer of Al, Cu, or the like. Heat resistance can be increased by usingan Al material into which an element such as Si, Ti, Ta, W, Mo, Cr, Nd,Sc or Y which prevents the generation of hillocks or whiskers on the Alfilm is added.

The source electrode and the drain electrode (including wires formed inthe same layer as the source electrode and the drain electrode) may beformed using a conductive metal oxide. As the conductive metal oxide,indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), an indiumoxide-tin oxide alloy (In₂O₃—SnO₂, abbreviated to ITO), indium oxide andzinc oxide (In₂O₃—ZnO), or a material which is added silicon or siliconoxide to the metal oxide material can be used. The metal conductive filmis not limited to a single layer containing the above-described elementand may be two or more layers. However, a material of the conductivefilm preferably has heat resistance that can withstand at least secondheat treatment performed later.

For the conductive film which is in contact with the oxide semiconductorlayers 404 a and 404 b, a material including metal with high oxygenaffinity is preferable. As the metal with high oxygen affinity, one ormore materials selected from titanium (Ti), manganese (Mn), magnesium(Mg), zirconium (Zr), beryllium (Be), and thorium (Th) are preferable.In this embodiment, a titanium film is used.

When the oxide semiconductor layer and the conductive film with highoxygen affinity are formed in contact with each other, the carrierdensity in the vicinity of the interface is increased and alow-resistance region is formed, whereby the contact resistance betweenthe oxide semiconductor layer and the conductive film can be reduced.This is because the conductive film with high oxygen affinity extractsoxygen from the oxide semiconductor layer and thus either or both alayer which includes metal in the oxide semiconductor layer in excess(such a layer is referred to as a composite layer) and an oxidizedconductive film are formed in the interface between the oxidesemiconductor layer and the conductive film. For example, in a structurewhere an In—Ga—Zn—O-based oxide semiconductor layer is in contact with atitanium film, an indium-excess layer and a titanium oxide layer areformed in the vicinity of the interface where the oxide semiconductorlayer is in contact with the titanium film in some cases. In othercases, either one of the indium-excess layer and the titanium oxidelayer is formed in the vicinity of the interface where the oxidesemiconductor layer is in contact with the titanium film. Theindium-excess layer which is an oxygen-deficient In—Ga—Zn—O-based oxidesemiconductor layer has high electric conductivity; therefore, thecontact resistance between the oxide semiconductor layer and theconductive film can be reduced.

Note that a titanium film or a titanium oxide film having conductivitymay be used as the conductive film which is in contact with the oxidesemiconductor layer. In that case, in the structure where theIn—Ga—Zn—O-based oxide semiconductor layer is in contact with thetitanium oxide film, an indium-excess layer might be formed in thevicinity of the interface where the oxide semiconductor layer is incontact with the titanium oxide film.

For the conductive film, a conductive material having alight-transmitting property with respect to visible light can be used.As the conductive material having a light-transmitting property withrespect to visible light, a transparent conductive oxide including anyof indium, tin, or zinc is preferable. For example, indium oxide (In₂O₃)or an indium oxide-tin oxide alloy (In₂O₃—SnO₂, abbreviated to ITO) canbe used. Alternatively, a transparent conductive oxide to which aninsulating oxide such as silicon oxide is added may be used. When atransparent conductive oxide is used for the conductive film, theaperture ratio of the display device can be improved.

As a formation method of the conductive film, an arc discharge ionplating method or a spray method may be employed. Alternatively, theconductive film may be formed by discharging a conductive nanopaste ofsilver, gold, copper, or the like by a screen printing method, anink-jet method, or the like and baking the nanopaste.

Then, a mask is formed over the conductive film by a photolithographymethod, an inkjet method, or the like and the conductive film is etchedusing the mask; thus, the source electrode and the drain electrode areformed (FIG. 1C). In this embodiment, a 200-nm-thick Ti film is formedby a sputtering method as the conductive film, and the conductive filmis selectively etched by a wet etching method or a dry etching methodusing a resist mask, whereby the second electrode layer 455 a, the thirdelectrode layer 455 b, the second electrode layer 455 c, and the thirdelectrode layer 455 d which function as the source electrodes and thedrain electrodes are formed.

Next, the second insulating layer 428 which covers the second electrodelayer 455 a, the third electrode layer 455 b, the second electrode layer455 c, the third electrode layer 455 d, and the exposed parts of theoxide semiconductor layers 404 a and 404 b is formed (FIG. 1D). Thethickness of the second insulating layer 428 is preferably greater thanor equal to 50 nm and less than or equal to 250 nm. The secondinsulating layer 428 includes an oxide insulating layer on the sidewhere the second insulating layer 428 is in contact with the oxidesemiconductor layer. As the oxide insulating layer in contact with theoxide semiconductor layer of the second insulating layer 428, an oxideinsulating layer such as a silicon oxide layer, a silicon oxynitridelayer, an aluminum oxide layer, a tantalum oxide layer, a yttrium oxidelayer, or a hafnium oxide layer is can be used.

The oxide insulating layer can be formed as appropriate with asputtering method or the like, i.e. a method with which impurities suchas moisture or hydrogen are not mixed into the oxide insulating layer.In this embodiment, a silicon oxide film is formed as the oxideinsulating layer by a sputtering method. The substrate temperature inthe deposition may be higher than or equal to room temperature and lowerthan or equal to 300° C. and in this embodiment, the substratetemperature in film formation is 100° C. In order to prevent entry of animpurity such as water or hydrogen in the deposition, it is preferableto perform pre-baking under reduced pressure at a temperature higherthan or equal to 150° C. and lower than or equal to 350° C. for greaterthan or equal to two minutes and less than or equal to ten minutesbefore the deposition, and to form an oxide insulating layer withoutexposure to the air. The silicon oxide film can be formed by asputtering method under a rare gas (typically, argon) atmosphere, anoxygen atmosphere, or a mixed atmosphere of a rare gas (typically,argon) and oxygen. As a target, a silicon oxide target or a silicontarget may be used. For example, with the use of a silicon target, asilicon oxide film can be formed by a sputtering method in an atmosphereof oxygen and a rare gas. During the formation of the oxide insulatinglayer in contact with the oxide semiconductor layer whose resistance isreduced, impurities such as moisture, a hydrogen ion, and OH⁻ areprevented from entering the oxide insulating layer.

A structure in which an inorganic insulating film is stacked over theoxide insulating layer so as to block entry of impurities such asmoisture, a hydrogen ion, OH⁻ to the oxide semiconductor layer from theoutside is preferable. As the inorganic insulating film stacked over theoxide insulating layer of the second insulating layer 428, a siliconoxide layer, a silicon oxynitride layer, a silicon nitride oxide layer,a silicon nitride layer, an aluminum oxide layer, a tantalum oxidelayer, or the like can be used.

In this embodiment, deposition is performed by a pulsed DC sputteringmethod with the use of a columnar polycrystalline, boron-doped silicontarget having a purity of 6N (with a resistivity of 0.01 Ω·cm) underconditions where the distance between the substrate and the target (T-Sdistance) is 89 mm, the pressure is 0.4 Pa, the direct current (DC)power is 6 kW, and the atmosphere is an oxygen atmosphere (theproportion of the oxygen flow is 100%). The film thickness is 300 nm. Itis preferable that a high-purity gas in which an impurity such ashydrogen, water, a hydroxyl group, or hydride is reduced toapproximately the ppm level or the ppb level be used as the sputteringgas for the deposition of the second insulating layer 428.

Next, second heat treatment is performed in an inert-gas atmosphere or anitrogen atmosphere (preferably at a temperature higher than or equal to200° C. and lower than or equal to 400° C., e.g., higher than or equalto 250° C. and lower than or equal to 350° C.). For example, the secondheat treatment is performed in a nitrogen atmosphere at 250° C. for onehour. Alternatively, RTA treatment may be performed at high temperaturefor a short time as in the first heat treatment. In the second heattreatment, since the oxide insulating layer is heated in contact withthe oxide semiconductor layer, oxygen is supplied to theoxygen-deficient portion of the oxide semiconductor layer whoseresistance is reduced by the first heat treatment, and thus the oxidesemiconductor layer can be changed into a high-resistance oxidesemiconductor layer (an i-type oxide semiconductor layer).

In this embodiment, the second heat treatment is performed afterformation of the silicon oxide film; however, the timing of the heattreatment is not limited to the timing immediately after formation ofthe silicon oxide film as long as it is after deposition of the siliconoxide film.

Then, a photolithography step is performed to form a resist mask, andthe second insulating layer 428 is etched to form a contact hole whichreaches the second electrode layer 455 d.

Next, after a conductive film is formed over the second insulating layer428, the fourth electrode layer 422 a, the fourth electrode layer 422 b,and a connection electrode layer 422 c which is connected to a pixelelectrode layer later are formed by a photolithography step performed onthe conductive film (FIG. 1E). As the conductive film, a single-layerstructure or a stacked-layer structure including a film containing anelement selected from Al, Cr, Cu, Ta, Ti, Mo, and W as a main componentcan be used. Note that in the case where the third electrode layer 455 dand the pixel electrode layer are directly connected, the connectionelectrode layer 422 c may be omitted.

In this embodiment, the fourth electrode layer 422 a of the transistor440A is used as a main gate electrode of the transistor. The potentialof the first electrode layer 421 a may be less than or equal to that ofthe fourth electrode layer 422 a, GND, or 0 V, or the first electrodelayer 421 a may be in a floating state.

In addition, the first electrode layer 421 b of the transistor 440B isused as a main gate electrode of the transistor. The potential of thefourth electrode layer 422 b may be less than or equal to that of thefirst electrode layer 421 b, GND, or 0 V, or the fourth electrode layer422 b may be in a floating state.

Each of the transistors has the four-terminal structure in which a pairof electrode layers which are provided on opposite sides from each otherwith respect to a channel formation region of an oxide semiconductorlayer, each with an insulating film arranged therebetween, and thus thereliability of the transistors can be improved. Specifically, in abias-temperature stress test (hereinafter, referred to as a BT test) forexamining reliability of a transistor, the amount of change in thresholdvoltage of the thin film transistor between before and after the BT testcan be reduced.

Note that as illustrated in FIG. 2, a structure in which the transistorwhich is used the first electrode layer is used as a main gate electrodeis not provided with the fourth electrode layer may be employed.

In FIG. 2, an example of a cross-sectional structure of a plurality oftransistors formed over a substrate with a circuit of a display deviceis illustrated. The transistor 440A illustrated in FIG. 2 has a kind offour-terminal structure in which a pair of electrode layers which areprovided on opposite sides from each other with respect to a channelformation region of an oxide semiconductor layer, each with aninsulating film arranged therebetween, and a transistor 450 is aninverted staggered transistor.

Note that the transistor 440A is preferably formed in a part of thedriver circuit arranged in a periphery of the pixel portion of thedisplay device, and the transistor 450 is preferably formed in part ofthe pixel circuit or the driver circuit or in the protective circuit.

The transistor 450 includes a first electrode layer 421 c, the firstinsulating layer 402, an oxide semiconductor layer 404 c including thecrystalline region 405 c, a second electrode layer 455 e, and a thirdelectrode layer 455 f over the substrate 400 having an insulatingsurface. In addition, the transistor 450 includes the second insulatinglayer 428 which is in contact with a crystalline region 405 c and coversthe transistor 450. The oxide semiconductor layer 404 c overlaps withthe first electrode layer 421 c with the first insulating layer 402provided therebetween. Further, the second electrode layer 455 e and thethird electrode layer 455 f are formed over the oxide semiconductorlayer 404 c so that part of the second electrode layer 455 e part of thethird electrode layer 455 f overlap with the oxide semiconductor layer404 c.

Note that a protective insulating layer may be formed so as to cover thetransistors 440A and 450B. The protective insulating layer is formedusing a silicon nitride film, a silicon nitride oxide film, an aluminumnitride film, or the like.

In the pixel portion, a planarization insulating layer may be formedover the fourth electrode layer 422 b. The planarization insulatinglayer can be formed of a heat-resistant organic material, such as anacrylic resin, polyimide, a benzocyclobutene-based resin, polyamide, oran epoxy resin. Other than such organic materials, it is also possibleto use a low-dielectric constant material (a low-k material), asiloxane-based resin, PSG (phosphosilicate glass), BPSG(borophosphosilicate glass), or the like. Note that the planarizationinsulating layer may be formed by stacking a plurality of insulatingfilms formed of these materials. Further, a color filter layer may beused as a planarization insulating layer.

A storage capacitor in which the first insulating layer 402 or adielectric layer including an oxide insulating layer is arranged betweena capacitor wiring which can be formed using the same material by thesame step as the first electrode layer 421 b and a capacitor electrodewhich can be formed using the same material by the same step as thefourth electrode layer 422 b may be formed over the same substrate. Thetransistor 440B and pixels including the storage capacitor are arrangedin matrix so that a pixel portion is formed and the substrate in whichthe driver circuit including the transistor 440A is arranged in theperiphery of the pixel portion can be one substrate used to manufacturean active matrix display device.

Further, in the case where a display device is manufactured by using thetransistors 440A and 440B, a power source supply line which iselectrically connected to the source electrode layer of the transistoris provided. The power source supply line intersects with a gate wiringand is formed using the same material by the same step as the connectionelectrode layer 422 c formed using a conductive film. Alternatively, thepower source supply line intersects with a source wiring and is formedusing the same material by the same step as the first electrode layer421 b.

Furthermore, in the case where a light-emitting device is manufactured,one electrode of the light-emitting element is electrically connected tothe source electrode layer or the drain electrode layer of the drivingtransistor, and a common potential line which is electrically connectedto the other electrode of the light-emitting element is provided. Notethat the common potential line is formed using the same material andthrough the same process as the connection electrode layer 422 c formedusing a metal conductive film. Alternatively, the common potential lineis formed using the same material by the same step as the firstelectrode layer 421 b.

The transistor including the oxide semiconductor layer whoseconcentration of hydrogen is reduced through the above-described processhas a characteristic of extremely small off-state current, which is1×10⁻¹³ A or less. As a transistor with small off-state current, forexample, there is a transistor using silicon carbide (e.g., 4H-SiC).There are some commonalities between an oxide semiconductor and 4H-SiC.The carrier concentration is one example of the commonalities betweenthe oxide semiconductor and 4H-SiC. In accordance with Fermi-Diracdistribution at room temperature, the minority carrier density in anoxide semiconductor is estimated to be approximately 10⁻⁷/cm³. Thisvalue of the minority carrier density is extremely small similarly tothat in 4H-SiC, which is 6.7×10⁻¹¹/cm³. When the minority carrierdensity of an oxide semiconductor is compared with the intrinsic carrierdensity of silicon (approximately 1.4×10¹⁰/cm³), it can be understoodwell that the minority carrier density of an oxide semiconductor issignificantly low. In addition, the energy band gap of the oxidesemiconductor is greater than or equal to 3.0 eV and less than or equalto 3.5 eV, and the energy band gap of 4H-SiC is 3.26 eV. Therefore, anoxide semiconductor has in common with silicon carbide in being a wideband-gap semiconductor.

On the other hand, there is a major difference between an oxidesemiconductor and silicon carbide, that is, the process temperature. Ingeneral, a semiconductor process using silicon carbide includes a heattreatment for activation at higher than or equal to 1500° C. and lowerthan or equal to 2000° C. At such a high temperature, a semiconductorsubstrate, a semiconductor element, or the like using a semiconductormaterial other than silicon carbide is damaged, and thus, it isdifficult to form a semiconductor element using silicon carbide over anintegrated circuit using a semiconductor material other than siliconcarbide. On the other hand, an oxide semiconductor can be depositedthrough heat treatment at higher than or equal to 300° C. and lower thanor equal to 500° C. (at a temperature lower than or equal to the glasstransition temperature, approximately 700° C. at a maximum). Therefore,it is possible to form a semiconductor element using an oxidesemiconductor after forming an integrated circuit using anothersemiconductor material.

In the case of using an oxide semiconductor, there is an advantage thatit is possible to use a substrate having low heat resistance such as aglass substrate, which is different from the case where silicon carbideis used. Moreover, an oxide semiconductor can be deposited without heattreatment at high temperature so that energy cost can be reducedsufficiently as compared with the case of using silicon carbide.

Note that a lot of research is done on properties of an oxidesemiconductor such as DOS (density of states); however, the researchdoes not include an idea that DOS itself is reduced sufficiently. In oneembodiment of the present invention, water and hydrogen havingpossibility of affecting the DOS in the energy band gap are eliminatedfrom an oxide semiconductor, so that a purified oxide semiconductor isformed. This idea is based on the idea that the DOS itself is reducedsufficiently. Therefore, manufacture of industrial products withextremely high quality can be realized.

Furthermore, oxygen may be supplied to a metal dangling bond generatedby oxygen deficiency so as to reduce the DOS due to oxygen defect,whereby more purified (i-type)oxide semiconductor can be formed. Forexample, an oxide film having an excessive amount of oxygen may beformed in close contact with a channel formation region, and oxygen maybe supplied from the oxide film so that DOS due to the oxygen defect canbe reduced.

It is said that the defect of an oxide semiconductor is due to the levelunder the conduction band greater than or equal to 0.1 eV and less thanor equal to 0.2 eV caused by an excessive amount of halogen, deep levelcaused by oxygen vacancy, or the like. Therefore, the technical idea ofremoving hydrogen completely and supplying oxygen sufficiently in orderto eliminate those defects would be reasonable.

In general, an oxide semiconductor is an n-type semiconductor; however,in one embodiment of the present invention, an impurity especially wateror hydrogen is removed so that an i-type oxide semiconductor isobtained. In this respect, it can be said that one embodiment of thedisclosed invention includes a novel technical idea because it isdifferent from an i-type semiconductor such as silicon added with animpurity.

A transistor using an oxide semiconductor has some characteristics.Here, the conduction mechanism of the oxide semiconductor is explainedwith reference to FIG. 23, FIGS. 24A and 24B, FIG. 25, and FIGS. 26A and26B. Note that the following description is just a consideration anddoes not deny the validity of the invention.

FIG. 23 is a cross-sectional view of an inverted staggered transistorwhich includes an oxide semiconductor. An oxide semiconductor layer (OS)is provided over a gate electrode (GE1) with a gate insulating film (GI)provided therebetween, and a source electrode (S) and a drain electrode(D) are provided over the oxide semiconductor layer. Furthermore, a backgate (GE2) is provided over the source electrode and the drain electrodewith an insulating layer provided therebetween.

FIGS. 24A and 24B are energy band diagrams (schematic diagrams) alongthe section A-A′ illustrated in FIG. 23. FIG. 24A illustrates the casewhere the voltage between the source and the drain is zero (V_(D)=0 V,the potential of the source and the potential of the drain are thesame). FIG. 24B illustrates a case where positive potential with respectto the source is applied to the drain (V_(D)>0).

FIG. 25 and FIGS. 26A and 26B are energy band diagrams (schematicdiagrams) along the section B-B′ in FIG. 23. FIG. 25 shows the casewhere the gate voltage is 0 V. FIG. 26A shows a state where a positivepotential (V_(G)>0) is applied to the gate (GE1), that is, a case wherethe transistor is in an on-state where carriers (electrons) flow betweenthe source and the drain. FIG. 26B shows a state where a negativepotential (V_(G)<0) is applied to the gate (GE1), that is, a case wherethe transistor is in an off state (where minority carriers do not flow).In the state where the oxide semiconductor has a thickness ofapproximately 50 nm and the donor concentration in the purified oxidesemiconductor is lower than or equal to 1×10¹⁸/cm³, a depletion layerexpands to the entire oxide semiconductor in the off state. That is, thetransistor can be regarded as a complete depletion transistor.

FIG. 27 shows a relation between the vacuum level and the work functionof a metal (ϕ_(M)) and a relation between the vacuum level and theelectron affinity of an oxide semiconductor (χ).

A metal is degenerated, so that the Fermi level is located in theconduction band. In contrast, a conventional oxide semiconductor is ofn-type, and the Fermi level (E_(f)) in that case is located closer tothe conduction band and is away from the intrinsic Fermi level (E_(i))that is located in the middle of the band gap. Note that it is knownthat part of hydrogen contained in the oxide semiconductor forms a donorand might be a factor that causes an oxide semiconductor to change intoan n-type oxide semiconductor.

On the other hand, an oxide semiconductor of the present invention is anintrinsic (i-type) or a substantially intrinsic oxide semiconductorwhich is obtained in such a manner that an oxide semiconductor ispurified so that an impurity other than main components of the oxidesemiconductor is prevented from being contained therein as much aspossible by removing hydrogen that is an n-type impurity from the oxidesemiconductor. In other words, a feature is that a purified i-type(intrinsic) semiconductor, or a semiconductor close thereto, is obtainednot by adding an impurity but by removing an impurity such as hydrogenor water as much as possible. This enables the Fermi level (E_(f)) to beat the same level as the intrinsic Fermi level (E_(i)).

It is said that in the case where the band gap (E_(g)) of the oxidesemiconductor is 3.15 eV, electron affinity (χ) is 4.3 eV. The workfunction of titanium (Ti) used for forming the source and drainelectrodes is substantially equal to the electron affinity (χ) of theoxide semiconductor. In that case, a Schottky barrier for electrons isnot formed at an interface between the metal and the oxidesemiconductor.

In other words, in the case where the work function of metal (GM) andthe electron affinity (χ) of the oxide semiconductor are equal to eachother and the metal and the oxide semiconductor are in contact with eachother, an energy band diagram (a schematic diagram) as illustrated inFIG. 24A is obtained.

In FIG. 24B, black circles (●) represent electrons. A dashed lineindicates movement of electrons when a voltage is not applied to a gate(V_(G)=0) in the state where a positive voltage is given to a drain(V_(D)>0), and a solid line indicates movement of electrons when apositive voltage is applied to a gate (V_(G)>0) in the state where apositive voltage is given to a drain (V_(D)>0). In the case where apositive voltage is applied to the gate (V_(G)>0), on application of apositive potential to the drain, the electron is injected into the oxidesemiconductor over the barrier (h) and flows toward the drain. In thatcase, the height of the barrier (h) changes depending on the gatevoltage and the drain voltage; in the case where a positive voltage isapplied to the gate (V_(G)>0) and a positive drain voltage is applied,the height of the barrier (h) is smaller than the height of the barrierin FIG. 24A where no voltage is applied, i.e., ½ of the band gap(E_(g)). In the case where a voltage is not applied to the gate, acarrier (electron) is not injected to the oxide semiconductor side froman electrode because of high potential barrier, so that a current doesnot flow, which means an off state. On the other hand, when positivevoltage is applied to the gate, potential barrier is reduced, and an onstate where current flows is shown.

The electron injected into the oxide semiconductor at this time flows inthe oxide semiconductor as illustrated in FIG. 26A. In FIG. 26B, when anegative potential is applied to the gate (GE1), the number of holesthat are minority carriers is substantially zero; thus, the currentvalue becomes a value as close to zero as possible.

As described above, an oxide semiconductor is made to be an intrinsic(i-type) semiconductor or made to be a substantially intrinsicsemiconductor by being purified so as not to contain impurities whichare not main components of the oxide semiconductor as much as possible.Therefore, interface characteristics between the gate insulating filmand the oxide semiconductor become obvious, and it is necessary toconsider the interface characteristics and the bulk characteristicsseparately. Therefore, it is necessary to use a gate insulating filmwhich can form a favorable interface with the oxide semiconductor. Forexample, it is preferable to use an insulating layer which is formed bya CVD method using high-density plasma generated with a power supplyfrequency from the VHF band to the microwave band or an insulating filmformed by a sputtering method.

When the oxide semiconductor is purified and the interface between theoxide semiconductor and the gate insulating film is favorable, even whenthe thin film transistor has a channel width W of 1×10⁴ μm and a channellength of 3 μm, an off-state current of 10⁻¹³ A or lower at roomtemperature and a subthreshold value (S value) of 0.1 V/dec. (thethickness of the gate insulating film: 100 nm) are greatly expected.

As described above, the oxide semiconductor is purified so as tominimize the amount of impurities that are not main components of theoxide semiconductor but contained in the oxide semiconductor, wherebyfavorable operation of the transistor can be obtained.

In this embodiment, a transistor includes a purified oxide semiconductorlayer. The oxide semiconductor layer includes a dense crystalline regionincluding nanocrystals in a surface portion of the oxide semiconductorlayer, and the dense crystalline region prevents the transistor fromchanging into an n-type transistor due to entry of moisture from thesuperficial portion to the inside of the purified oxide semiconductorlayer or elimination of oxygen. Such a transistor having a four-terminalstructure in which a pair of electrode layers which are provided onopposite sides from each other with respect to the purified oxidesemiconductor layer, each with an insulating film arranged therebetweenis characterized by a positive threshold voltage and an extremely smalloff-state current.

In the case where the fourth electrode layer is used as a main gateelectrode, a channel is formed in a region which is provided between aregion in contact with the second electrode layer of the oxidesemiconductor layer and a region in contact with the third electrodelayer of the oxide semiconductor layer, which is in contact with thesecond insulating layer, and which overlaps with the fourth electrodelayer. Note that a region in which the channel is formed is acrystalline region of the oxide semiconductor as well, and includes thecrystal grains in which c-axis is oriented in an almost verticaldirection with respect to the surface of the oxide semiconductor layer.For example, in the case where an In—Ga—Zn—O-based oxide semiconductormaterial is used for the oxide semiconductor layer, nanocrystals arearranged so that c-axis of In₂Ga₂ZnO₇ is in a vertical direction withrespect to a substrate plane (or a surface of the oxide semiconductorlayer), whereby current flows through the transistor in a b-axisdirection (or an a-axis direction) of In₂Ga₂ZnO₇. Therefore, thetransistor in which the fourth electrode layer is used as a main gateelectrode exhibits high dynamic characteristics (on characteristics orfrequency characteristics (referred to as f characteristics)), and thuscan favorably be used as a transistor for a driver circuit to whichhigh-speed operation is required.

In the case where the first electrode layer is used as a main gateelectrode, a channel is formed in a region which is provided between aregion in contact with the second electrode layer of the oxidesemiconductor layer and a region in contact with the third electrodelayer of the oxide semiconductor layer, which is in contact with thefirst insulating layer, and where overlaps with the first electrodelayer. Note that in the oxide semiconductor layer which becomes i-typeor becomes substantially i-type (an oxide semiconductor layer which ispurified) due to removal of an impurity, the carrier concentration issuppressed. In addition, a dense crystalline region includingnanocrystals exists on the side opposite to a channel formation regionof the oxide semiconductor layer, and thus, a change to an n-type, whichis attributed to entry of moisture from the superficial portion orelimination of oxygen, can be prevented. Therefore, the transistor inwhich the first electrode layer is used as a main gate electrode has anextremely small off-state current and excellent reliability, and thuscan favorably be used as a transistor for a pixel portion to which areduction of a leakage current is required.

As described above, by selecting a mainly used gate electrode, electriccharacteristics of the transistor having a four-terminal structure inwhich a pair of electrode layers which are provided on opposite sidesfrom each other with respect to a channel formation region of an oxidesemiconductor layer including a crystalline region in a surface portionof the oxide semiconductor layer, each with an insulating film arrangedtherebetween can be selected.

A plurality of transistors each having a four-terminal structure inwhich a pair of electrode layers are formed over one substrate in achannel formation region of an oxide semiconductor layer including acrystalline region in a surface portion of the oxide semiconductorlayer. The electrode layers are provided on opposite sides from eachother with respect to the oxide semiconductor layer, each with aninsulating film arranged therebetween. A mainly used gate electrode isselected, and thus, a plurality of transistors having differentcharacteristics and provided over one substrate can be operated.

In addition, a semiconductor device including a driver circuit which iscapable of high-speed operation and a pixel portion whose powerconsumption is suppressed can be manufactured over one substrate.

Note that in the transistor which is one embodiment of the presentinvention, the mainly used gate electrode is not necessarily fixed tothe first electrode layer or the fourth electrode layer. The mainly usedgate electrode can be changed as appropriate in accordance with theoperation state and the operation load of the circuit.

Note that this embodiment can be freely combined with any of the otherembodiments.

Embodiment 2

In Embodiment 2, an example of forming an inverter circuit of a drivercircuit using two transistors each having a four-terminal structure inwhich a pair of electrode layers which are provided on opposite sidesfrom each other with respect to a channel formation region of an oxidesemiconductor layer, each with an insulating film arranged therebetweenis described with reference to FIGS. 3A, 3B, and 3C. Transistors in FIG.3A are the same as the transistors 440A and 440B in FIG. 1E ofEmbodiment 1, and thus the same parts are denoted by the same referencenumerals.

A driver circuit for driving a pixel portion may be provided in theperiphery of the pixel portion, and is formed using an inverter circuit,a capacitor, a resistor, or the like. In one embodiment of the invertercircuit, the inverter circuit is formed using two n-channel transistorsin combination. For example, there are an inverter circuit having acombination of an enhancement transistor and a depletion transistor(hereinafter, referred to as an EDMOS circuit) and an inverter circuithaving a combination of two enhancement transistors (hereinafter,referred to as an EEMOS circuit).

FIG. 3A illustrates a cross-sectional structure of the inverter circuitof the driver circuit. Since a first transistor 440A and a secondtransistor 440B can be formed by a method similar to the methoddescribed in Embodiment 1, detailed description is omitted. Note that itis preferable to form a contact hole 408 in a second insulating layer428 and then, form a fourth electrode layer 422 a and a fourth electrodelayer 422 b, and directly connect a second wiring 410 b and the fourthelectrode layer 422 b each connected to a second electrode layer 455 cthrough the contact hole 408. The number of contact holes needed for aconnection is small, so that not only the electric resistance but alsoan area occupied by the contact hole can be reduced.

A first wiring 410 a connected to a second electrode layer 455 a in thefirst transistor 440A is a power supply line to which negative voltageVDL is applied (a negative power supply line). This power supply linemay be a power supply line with a ground potential (a ground potentialpower supply line).

Further, a third wiring 410 c connected to a third electrode layer 455 din the second transistor 440B is a power supply line to which positivevoltage VDH is applied (a positive power supply line).

Further, FIG. 3C is a top view of the inverter circuit of the drivercircuit. In FIG. 3C, a cross section taken along the chain line Z1-Z2corresponds to FIG. 3A.

Further, an equivalent circuit of the EDMOS circuit is illustrated inFIG. 3B. The circuit connection illustrated in FIG. 3B corresponds tothat illustrated in FIG. 3A. An example in which the first transistor440A is an enhancement n-channel transistor and the second transistor440B is a depletion n-channel transistor is illustrated.

In Embodiment 2, a first electrode and a fourth electrode which areprovided on opposite sides from each other with respect to a channelformation region of a purified oxide semiconductor layer, each with aninsulating film arranged therebetween are used in order to control thethreshold value of the first transistor 440A and the second transistor440B. Specifically, voltage is applied to each of the first electrodeand the fourth electrode so that the first transistor 440A becomes anenhancement transistor and the second transistor 440B becomes adepletion transistor.

Note that although the example in which the second wiring 410 b isdirectly connected to the fourth electrode layer 422 b through thecontact hole 408 formed in the second insulating layer 428 isillustrated in FIGS. 3A and 3C, without particular limitations, aconnection electrode may be additionally provided so as to electricallyconnect the second wiring 410 b and the fourth electrode layer 422 b.Further, although the fourth electrode layer of the second transistor440B is used as a main gate electrode in this embodiment, the firstelectrode layer of the second transistor 440B may be used as a main gateelectrode. In such a case, it is not necessary that the contact hole 408is provided in the second insulating layer 428, and a contact holeconnects to the second electrode layer 455 c and the first electrodelayer 421 b is formed in the first insulating layer 402.

As described above, the inverter circuit can be formed using twotransistors with the four-terminal structure in which a pair ofelectrode layers which are provided on opposite sides from each otherwith respect to a channel formation region of an oxide semiconductorlayer, each with an insulating film arranged therebetween. The thresholdvalue of the transistors is controlled by using the first electrodelayer and the fourth electrode layer of the dual-gate structure, wherebythe enhancement transistor and the depletion transistor can be formedover one substrate without forming oxide semiconductor filmsadditionally, and thus the manufacturing process is simple.

In addition, the inverter circuit to which the transistor of oneembodiment of the present invention in which the fourth electrode layeris used as a main gate electrode has favorable dynamic characteristics.

In addition, this embodiment can be freely combined with any of theother embodiments.

Embodiment 3

In this embodiment, an example of manufacturing a pulse output circuitusing a transistor in which a pair of electrode layers which areprovided on opposite sides from each other with respect to a channelformation region of an oxide semiconductor layer, each with aninsulating film arranged therebetween. Further, an example ofmanufacturing a shift register by connecting a plurality of such pulseoutput circuits will be described with reference to FIGS. 4A to 4C andFIGS. 5A and 5B.

Note that a transistor is an element having at least three terminals ofa gate, a drain, and a source. The transistor has a channel regionbetween a drain region and a source region, and current can flow throughthe drain region, the channel region, and the source region. Here, sincethe source and the drain of the transistor may change depending on thestructure, the operating condition, and the like of the transistor, itis difficult to define which is a source or a drain. Therefore, regionsfunctioning as source and drain are not called the source and the drainin some cases. In such a case, for example, one of the source and thedrain may be referred to as a first terminal and the other may bereferred to as a second terminal.

FIG. 4A illustrates a structure of a shift register. The shift registerincludes a first to N-th pulse output circuits 10_1 to 10_N (N is anatural number greater than or equal to 3).

The first to N-th pulse output circuits 10_1 to 10_N are connected to afirst wiring 11, a second wiring 12, a third wiring 13, and a fourthwiring 14. A first clock signal CK1, a second clock signal CK2, a thirdclock signal CK3, and a fourth clock signal CK4 are supplied from thefirst wiring 11, the second wiring 12, the third wiring 13, and thefourth wiring 14, respectively.

Note that a clock signal (CK) is a signal that alternates between an Hlevel (also referred to as an H signal or a signal at high power supplypotential level) and an L level (also referred to as an L signal or asignal at low power supply potential level) at regular intervals. Here,the first to fourth clock signals (CK1) to (CK4) are delayed by ¼ periodsequentially. In this embodiment, driving or the like of the pulseoutput circuits is controlled with the first to fourth clock signals(CK1) to (CK4). Note that the clock signal is also referred to as GCK orSCK in some cases depending on a driver circuit to which the clocksignal is input; the clock signal is referred to as CK in the followingdescription.

Each of the first to N-th pulse output circuits 10_1 to 10_N includes afirst input terminal 21, a second input terminal 22, a third inputterminal 23, a fourth input terminal 24, a fifth input terminal 25, afirst output terminal 26, and a second output terminal 27 (see FIG. 4B).Although not illustrated, each of the first to N-th pulse outputcircuits 10_1 to 10_N is connected to a power supply line 51, a powersupply line 52, and a power supply line 53.

The first input terminal 21, the second input terminal 22, and the thirdinput terminal 23 of each of the pulse output circuits are electricallyconnected to any of the first to fourth wirings 11 to 14. For example,in the first pulse output circuit 10_1 in FIG. 4A, the first inputterminal 21 is electrically connected to the first wiring 11, the secondinput terminal 22 is electrically connected to the second wiring 12, andthe third input terminal 23 is electrically connected to the thirdwiring 13. In the second pulse output circuit 10_2, the first inputterminal 21 is electrically connected to the second wiring 12, thesecond input terminal 22 is electrically connected to the third wiring13, and the third input terminal 23 is electrically connected to thefourth wiring 14.

A start pulse SP1 (a first start pulse) is input from a fifth wiring 15to the first pulse output circuit 10_1. To the n-th pulse output circuit10_n of the second or subsequent stage (n is a natural number greaterthan or equal to 2 and less than or equal to N), a signal from the pulseoutput circuit of the preceding stage (such a signal is referred to as apreceding-stage signal OUT(n−1)) (n is a natural number greater than orequal to 2) is input.

In addition, a signal from the third pulse output circuit 10_3 is inputto the first pulse output circuit 10_1 in the two stages before thethird pulse output circuit 10_3. In a similar manner, a signal from the(n+2)-th pulse output circuit 10_(n+2) in two stages after the n-thpulse output circuit 10_n (such a signal is referred to as asubsequent-stage signal OUT(n+2)) is input to the n-th pulse outputcircuit 10_n in the second or subsequent stage. Therefore, from thepulse output circuit in each stage, a first output signal (OUT(1)(SR) toOUT(N)(SR)) to be input to a pulse output circuit in the next stageand/or in two stages before the pulse output circuit and a second outputsignal (OUT(1) to OUT(N)) for electrical connection to another wiring orthe like are output.

That is, in the first pulse output circuit 10_1, the first clock signalCK1 is input to the first input terminal 21; the second clock signal CK2is input to the second input terminal 22; the third clock signal CK3 isinput to the third input terminal 23; a start pulse is input to thefourth input terminal 24; a subsequent-stage signal OUT(3) is input tothe fifth input terminal 25; the first output signal OUT(1)(SR) isoutput from the first output terminal 26; and the second output signalOUT(1) is output from the second output terminal 27.

As illustrated in FIG. 4A, the subsequent-stage signal OUT(n+2) is notinput to the last two stages of the shift register (10_N-1, 10_N). Forexample, a second start pulse SP2 from a sixth wiring 16 and a thirdstart pulse SP3 from a seventh wiring 17 may be input to the pulseoutput circuits 10_N-1 and 10_N, respectively. Alternatively, a signalwhich is additionally generated in the shift register may be input. Forexample, an (N+1)-th pulse output circuit 10_(N+1) and an (N+2)-th pulseoutput circuit 10_(N+2) which do not contribute to output of pulses tothe pixel portion (such circuits are also referred to as dummy stages)may be provided so that signals corresponding to the second start pulse(SP2) and the third start pulse (SP3) are generated in the dummy stages.

Next, a structure of a pulse output circuit of an embodiment of thepresent invention will be described with reference to FIG. 4C.

The first to N-th pulse output circuits 10_1 to 10_N are connected tothe power supply line 51, the power supply line 52, and the power supplyline 53. A first high power supply potential VDD, a second high powersupply potential VCC, and a low power supply potential VSS are suppliedthrough the power supply line 51, the power supply line 52, and thepower supply line 53, respectively. Here, the relation of the powersupply potentials of the power supply lines 51 to 53 is for example asfollows: the first high power supply potential VDD is higher than orequal to the second high power supply potential VCC, and the second highpower supply potential VCC is higher than the low power supply potentialVSS. By making the potential VCC of the power supply line 52 lower thanthe potential VDD of the power supply line 51, a potential applied to agate electrode of a transistor can be lowered, shift in thresholdvoltage of the transistor can be reduced, and deterioration of thetransistor can be suppressed without an adverse effect on the operationof the transistor.

Note that the first to fourth clock signals (CK1) to (CK4) eachalternate between an H level and an L level at regular intervals; theclock signal at the H level is VDD and the clock signal at the L levelis VSS.

The first to N-th pulse output circuits 10_1 to 10_N each include afirst to eleventh transistors 31 to 41 (see FIG. 4C). In thisembodiment, a pulse output circuit is formed by forming two kinds oftransistors over one substrate. Since the first to N-th pulse outputcircuits 10_1 to 10_N included in the shift register exemplified in thisembodiment have the same configuration, the structure and operation ofthe first pulse output circuit 10_1 are described here.

The first pulse output circuit 10_1 includes a first to eleventhtransistors 31 to 41. The first to eleventh transistors 31 to 41 aren-channel transistors each including a purified oxide semiconductorlayer.

Note that in a purified oxide semiconductor layer of one embodiment ofthe present invention, a dense crystalline region including nanocrystalsexists in a surface portion of the oxide semiconductor layer andprevents the transistor from changing into an n-type transistor due toentry of moisture from the superficial portion or elimination of oxygen.Such a transistor having the four-terminal structure in which a pair ofelectrode layers which are provided on opposite sides from each otherwith respect to a purified oxide semiconductor layer, each with aninsulating film arranged therebetween is characterized by a positivethreshold voltage and an extremely small off-state current.

A transistor in which a first electrode layer arranged on the substrateside with a first insulating layer provided therebetween is used as amain gate electrode and where the surface portion of the oxidesemiconductor layer in which the crystalline region is formed is on theback channel side has an extremely small off-state current and excellentreliability. Therefore, in this embodiment, the transistor in which thefirst electrode layer is applied to a main gate electrode is used as asecond transistor 32 and a fifth transistor 35.

Note that the transistor in which the first electrode layer is used as amain gate electrode is also suitable for transistors, to a gateelectrode of which signals are directly input from the outside, in apulse output circuit and a shift register formed by connecting aplurality of such pulse output circuits. For example, in the case of thefirst pulse output circuit 10_1, the transistor in which the firstelectrode layer is used as a main gate electrode can be suitably appliedto the first transistor 31 and the fifth transistor 35 which areconnected to the fourth input terminal 24, to which a start pulse isinput from the outside. The transistor in which the first electrodelayer is used as a main gate electrode has a high withstand voltagebetween the gate and the source and between the gate and the drain;therefore, problems such as the shift in threshold value of thetransistor included in the circuit caused by abnormal input such asstatic electricity can be reduced.

A transistor in which a fourth electrode layer arranged on the oppositeside to the substrate with a second insulating layer providedtherebetween is used as a main gate electrode and in which a channelformation region is included in the surface portion of the oxidesemiconductor layer where the crystalline region is formed has highdynamic characteristics. Therefore, in this embodiment, the transistorin which the fourth electrode layer is used as a main gate electrode isapplied to a third transistor 33, a sixth transistor 36, a tenthtransistor 40, and an eleventh transistor 41.

Note that each of the transistors in which the fourth electrode layer isused as a main gate electrode and the transistor in which the firstelectrode layer is used as a main gate electrode can be manufactured inaccordance with the method described in Embodiment 1. Therefore,detailed description is omitted in this embodiment.

As the first transistor 31, the fourth transistor 34, the seventhtransistor 37 to the ninth transistor 39, either the transistor in whichthe first electrode layer is used as a main gate electrode or thetransistor in which the fourth electrode layer is used as a main gateelectrode may be used. In this embodiment, the transistor in which thefirst electrode layer is used as a main gate electrode is applied.

In FIG. 4C, a first terminal of the first transistor 31 is electricallyconnected to the power supply line 51, a second terminal of the firsttransistor 31 is electrically connected to a first terminal of the ninthtransistor 39, and a gate electrode of the first transistor 31 iselectrically connected to the fourth input terminal 24. A first terminalof the second transistor 32 is electrically connected to the powersupply line 53, a second terminal of the second transistor 32 iselectrically connected to the first terminal of the ninth transistor 39,and a gate electrode of the second transistor 32 is electricallyconnected to a gate electrode of the fourth transistor 34. A firstterminal of the third transistor 33 is electrically connected to thefirst input terminal 21, and a second terminal of the third transistor33 is electrically connected to the first output terminal 26. A firstterminal of the fourth transistor 34 is electrically connected to thepower supply line 53, and a second terminal of the fourth transistor 34is electrically connected to the first output terminal 26. A firstterminal of the fifth transistor 35 is electrically connected to thepower supply line 53, and a second terminal of the fifth transistor 35is electrically connected to the gate electrode of the second transistor32 and the gate electrode of the fourth transistor 34, and a gateelectrode of the fifth transistor 35 is electrically connected to thefourth input terminal 24. A first terminal of the sixth transistor 36 iselectrically connected to the power supply line 52, a second terminal ofthe sixth transistor 36 is electrically connected to the gate electrodeof the second transistor 32 and the gate electrode of the fourthtransistor 34, and a gate electrode of the sixth transistor 36 iselectrically connected to the fifth input terminal 25. A first terminalof the seventh transistor 37 is electrically connected to the powersupply line 52, a second terminal of the seventh transistor 37 iselectrically connected to a second terminal of the eighth transistor 38,and a gate electrode of the seventh transistor 37 is electricallyconnected to the third input terminal 23. A first terminal of the eighthtransistor 38 is electrically connected to the gate electrode of thesecond transistor 32 and the gate electrode of the fourth transistor 34,and a gate electrode of the eighth transistor 38 is electricallyconnected to the second input terminal 22. The first terminal of theninth transistor 39 is electrically connected to the second terminal ofthe first transistor 31 and the second terminal of the second transistor32, a second terminal of the ninth transistor 39 is electricallyconnected to a gate electrode of the third transistor 33 and a gateelectrode of the tenth transistor 40, and a gate electrode of the ninthtransistor 39 is electrically connected to the power supply line 52. Afirst terminal of the tenth transistor 40 is electrically connected tothe first input terminal 21, a second terminal of the tenth transistor40 is electrically connected to the second output terminal 27, and thegate electrode of the tenth transistor 40 is electrically connected tothe second terminal of the ninth transistor 39. A first terminal of theeleventh transistor 41 is electrically connected to the power supplyline 53, a second terminal of the eleventh transistor 41 is electricallyconnected to the second output terminal 27, and a gate electrode of theeleventh transistor 41 is electrically connected to the gate electrodeof the second transistor 32 and the gate electrode of the fourthtransistor 34.

In FIG. 4C, the point at which the gate electrode of the thirdtransistor 33, the gate electrode of the tenth transistor 40, and thesecond terminal of the ninth transistor 39 are connected is referred toas a node A. Further, the point at which the gate electrode of thesecond transistor 32, the gate electrode of the fourth transistor 34,the second terminal of the fifth transistor 35, the second terminal ofthe sixth transistor 36, the first terminal of the eighth transistor 38,and the gate electrode of the eleventh transistor 41 are connected isreferred to as a node B. A capacitor having one electrode electricallyconnected to the node B may be additionally provided in order to hold apotential of the node B. Specifically, a capacitor having one electrodeelectrically connected to the node B and the other electrodeelectrically connected to the power supply line 53 may be provided.

Next, operation of a pulse output circuit illustrated in FIG. 5A will bedescribed with reference to FIG. 5B, FIGS. 6A to 6D, FIGS. 7A to 7D, andFIGS. 8A and 8B. Specifically, operation of the pulse output circuitwill be described in separate periods: a first period 61, a secondperiod 62, a third period 63, a fourth period 64, and a fifth period 65in a timing chart of FIG. 5B. In FIGS. 6A to 6D and FIGS. 7A to 7D,transistors indicated by a solid line is in an ON state (a conductivestate) and transistors indicated by a broken line is in an OFF state (anon-conductive state).

Here, the output of the first pulse output circuit 10_1 is described.The first input terminal 21 of the first pulse output circuit 10_1 iselectrically connected to the first wiring 11 through which the firstclock signal (CK1) is supplied, the second input terminal 22 iselectrically connected to the second wiring 12 through which the secondclock signal (CK2) is supplied, and the third input terminal 23 iselectrically connected to the third wiring 13 through which the thirdclock signal (CK3) is supplied.

In the following description, the first to eleventh transistors 31 to 41are n-channel transistors and are turned on when the gate-source voltage(Vgs) exceeds the threshold voltage (Vth).

Further, for simplicity, description is made under the assumption thatVSS is 0 here; however, the present invention is not limited thereto. Adifference between VDD and VCC and a difference between VCC and VSS (inthe case where the following relation is satisfied: VDD>VCC) are eachhigher than the threshold voltages of the transistors, that is, suchdifferences can make the transistors in an ON state (a conductivestate). When the potential of the power supply line 52 is lower than thepotential of the power supply line 51, a potential applied to the gateelectrodes of the second transistor 32, the fourth transistor 34, theninth transistor 39, and the eleventh transistor 41 can be suppressed tobe low; the shift of the threshold value of the second transistor 32,the fourth transistor 34, the ninth transistor 39, and the eleventhtransistor 41 in the pulse output circuit can be reduced; anddeterioration can be suppressed.

In the first period 61, the first start pulse (SP1) changes into an Hlevel, so that the first transistor 31 and the fifth transistor 35,which are electrically connected to the fourth input terminal 24 of thefirst pulse output circuit 10_1 to which the first start pulse (SP1) isinput, change into a conductive state. Since the third clock signal(CK3) is also at an H level, the seventh transistor 37 is also turnedon. In addition, the second high power supply potential VCC is appliedto the gate of the ninth transistor 39, thereby turning on the ninthtransistor 39 (see FIG. 6A).

At this time, since the first transistor 31 and the ninth transistor 39are on, the potential of the node A is increased. Meanwhile, since thefifth transistor 35 is on, the potential of the node B decreases.

The second terminal of the first transistor 31 serves as a source, andthe potential of the second terminal of the first transistor 31 has sucha value that is obtained by subtracting the threshold voltage of thefirst transistor 31 from the potential of the first power supply line51, which can be expressed by VDD−Vth31 (Vth31 is a threshold voltage ofthe first transistor 31). When (VDD−Vth31) is higher than or equal to(VCC−Vth39) where Vth39 is a threshold voltage of the ninth transistor39, the potential of the node A is (VCC−Vth39), whereby the ninthtransistor 39 is turned off. The node A is in a floating state,maintaining the potential (VCC−Vth39). When (VDD−Vth31) is lower than(VCC−Vth39), the ninth transistor 39 is not turned off and the potentialof the node A is increased to (VDD−Vth31).

In this embodiment, since the first transistor 31 to the eleventhtransistor 41 all have the same threshold voltage Vth0, the potential ofthe node A is (VCC−Vth0) and the ninth transistor 39 is turned off. Thenode A is in a floating state, maintaining the potential (VCC−Vth0).

Here, the potential of the gate electrode of the third transistor 33 is(VCC−Vth0). The gate-source voltage of the third transistor 33 is higherthan the threshold voltage thereof, that is, the following relation isobtained: VCC−Vth0>Vth33 (Vth33 is a threshold voltage of the thirdtransistor 33 and is, in this embodiment, Vth0). Accordingly, the thirdtransistor 33 is turned on.

In the second period 62, the first clock signal (CK1) supplied to thefirst input terminal 21 of the first pulse output circuit 10_1 ischanged from an L level to an H level. Since the third transistor 33 hasalready been on, current flows between the source and the drain, and thepotential of the output signal (OUT(1)(SR)) output from the outputterminal 26, that is, the potential of the second electrode (the sourceelectrode in this case) of the third transistor 33 starts increasing.There exists capacitive coupling due to parasitic capacitance betweenthe gate and the source and the channel capacitance of the thirdtransistor 33, and with the increase in the potential of the outputterminal 26, the potential of the gate electrode of the third transistor33 which is in a floating state is increased (bootstrap operation).Finally, the potential of the gate electrode of the third transistor 33becomes higher than (VDD+Vth33) and the potential of the output terminal26 becomes equal to VDD (see FIG. 5B and FIG. 6B).

At this time, since the fourth input terminal 24 of the first pulseoutput circuit 10_1 has an H level due to the supply of the first startpulse (SP1), the fifth transistor 35 is on, and the L level ismaintained at the node B. Accordingly, when the potential of the outputterminal 26 rises from an L level to an H level, a malfunction due tocapacitive coupling between the output terminal 26 and the node B can besuppressed.

Next, in the first half of the third period 63, the first start pulse(SP1) changes into an L level, so that the first transistor 31 and thefifth transistor 35 are turned off. The first clock signal (CK1) keepsthe H level from the second period 62, and the potential of the node Adoes not change as well; therefore, an H level signal is supplied to thefirst electrode of the third transistor 33 (see FIG. 6C). In the firsthalf of the third period 63, each transistor connected to the node B isturned off, so that the node B is in a floating state. However, thepotential of the output terminal 26 does not change, so that theinfluence from a malfunction due to capacitive coupling between the nodeB and the output terminal 26 is negligible.

Note that by providing the ninth transistor 39 having the gate to whichthe second high power supply potential VCC is applied as illustrated inFIG. 5A, the following advantages before and after the bootstrapoperation are obtained.

Without the ninth transistor 39 having the gate electrode to which thesecond high power supply potential VCC is applied, if the potential ofthe node A is raised by the bootstrap operation, the potential of thesource which is the second terminal of the first transistor 31 rises toa value higher than the first high power supply potential VDD. Then, thefirst terminal of the first transistor 31, that is, the terminal on thepower supply line 51 side, comes to serve as a source of the firsttransistor 31. Consequently, in the first transistor 31, a high biasvoltage is applied and thus significant stress is applied between thegate and the source and between the gate and the drain, which mightcause deterioration of the transistor.

On the other hand, with the ninth transistor 39 having the gateelectrode to which the second high power supply potential VCC isapplied, increase in the potential of the second terminal of the firsttransistor 31 can be prevented even when the potential of the node A israised by the bootstrap operation. In other words, provision of theninth transistor 39 can lower the level of negative bias voltage appliedbetween the gate and the source of the first transistor 31. Thus, thecircuit configuration in this embodiment can reduce negative biasvoltage applied between the gate and the source of the first transistor31, so that deterioration of the first transistor 31 due to stress canbe reduced.

Note that the ninth transistor 39 can be provided anywhere as long asthe first terminal and the second terminal of the ninth transistor 39are connected between the second terminal of the first transistor 31 andthe gate of the third transistor 33. Note that when the shift registerincluding a plurality of pulse output circuits in this embodiment isincluded in a signal line driver circuit for which higher dynamiccharacteristics are required than a scan line driver circuit, the ninthtransistor 39 may be omitted, which is advantageous in that the numberof transistors is reduced.

In the latter half of the third period 63, the third clock signal (CK3)is changed into an H level, whereby the seventh transistor 37 is turnedon. The second clock signal (CK2) keeps the H level from the first halfof the third period 63, and the eighth transistor 38 is on, so that thepotential of the node B is increased to VCC.

Since the potential of the node B is increased, the second transistor32, the fourth transistor 34, and the eleventh transistor 41 change intoan ON state, so that the potential of the output terminal 27 (OUT(1))becomes an L level.

In the latter half of the third period 63, the second transistor 32 isturned on and an L level signal is supplied to the first terminal of theninth transistor 39; thus, the ninth transistor 39 changes into an ONstate and the potential of the node A is decreased.

Since the fourth transistor 34 changes into an ON state, the potentialof the output terminal 26 is decreased (see FIG. 6D).

In the first half of the fourth period 64, the second clock signal (CK2)is changed from an H level to an L level, whereby the eighth transistor38 is turned off However, because the fifth input terminal 25 (OUT(3))keeps the H level to keep the sixth transistor 36 in an ON state, thenode B maintains VCC (see FIG. 7A).

In the latter half of the fourth period 64, the fifth input terminal 25(OUT(3)) of the first pulse output circuit 10_1 changes into an L level,whereby the sixth transistor 36 is turned off (see FIG. 7B). At thistime, the node B changes from a state of holding a VCC level into afloating state. Accordingly, the second transistor 32, the fourthtransistor 34, and the eleventh transistor 41 keep an ON state. Notethat as illustrated in FIG. 5B, the potential of the node B is decreasedfrom the VCC level due to an off-state current of a transistor or thelike.

Then, the circuit cyclically repeats the operation. Such a period isreferred to as a fifth period 65 (see FIG. 7C and FIG. 7D). In a certainperiod in the fifth period 65 (a period when the second clock signal(CK2) and the third clock signal (CK3) are both at an H level), theseventh transistor 37 and the eighth transistor 38 are turned on and asignal at a VCC level is regularly supplied to the node B (see FIG. 7D).

With the structure in which a signal at a VCC level is regularlysupplied to the node B in the fifth period 65, a malfunction of thepulse output circuit can be suppressed. In addition, by regularlyturning on or off the seventh transistor 37 and the eighth transistor38, a shift of a threshold value of the transistor can be reduced.

In the fifth period 65, in the case where the potential of the node B isdecreased during the time when the signal at a VCC level is not suppliedfrom the second power supply line 52 to the node B, the node B may beprovided with a capacitor in advance to reduce the decrease in thepotential of the node B.

Although the second input terminal 22 is connected to the gate electrodeof the eighth transistor 38 and the third input terminal 23 is connectedto the seventh transistor 37 in the drawing, the connection relation maybe changed so that the clock signal that has been supplied to the gateelectrode of the eighth transistor 38 is supplied to the gate electrodeof the seventh transistor 37 and the clock signal that has been suppliedto the gate electrode of the seventh transistor 37 is supplied to thegate electrode of the eighth transistor 38. Even with this structure, asimilar effect can be obtained.

In the pulse output circuit illustrated in FIG. 5A, if potentials of thesecond input terminal 22 and the third input terminal 23 are controlledso that the state is changed from the state where the seventh transistor37 and the eighth transistor 38 are both on, to the state where theseventh transistor 37 is off and the eighth transistor 38 is still on,and then to the state where the seventh transistor 37 and the eighthtransistor 38 are both off, a fall in the potential of the node B occurstwice because of the fall in the potential of the gate electrode of theseventh transistor 37 and the fall in the potential of the gateelectrode of the eighth transistor 38.

On the other hand, in the pulse output circuit illustrated in FIG. 5A,when the state is changed from the state where the seventh transistor 37and the eighth transistor 38 are both on, to the state where the seventhtransistor 37 is still on and the eighth transistor 38 is off, and thento the state where the seventh transistor 37 and the eighth transistor38 are both off as illustrated in FIG. 5B, the fall in the potential ofthe node B occurs only once because of the fall in the potential of thegate electrode of the eighth transistor 38. Thus, the number of falls inthe potential can be reduced to one.

In other words, it is preferable that the clock signal is supplied fromthe third input terminal 23 to the gate electrode of the seventhtransistor 37 and the clock signal is supplied from the second inputterminal 22 to the gate electrode of the eighth transistor 38 becausethe fluctuation in the potential of the node B can be reduced andtherefore noise can be reduced.

In such a manner, a signal at a VCC level is regularly supplied to thenode B in a period during which the potentials of the first outputterminal 26 and the second output terminal 27 are held at an L level;thus, a malfunction of the pulse output circuit can be suppressed.

In the latter half of the fourth period 64, the node B in the pulseoutput circuit described in this embodiment changes from a state ofholding a VCC level into a floating state. There is a fear that thepotential of the node B in the floating state may be decreased from theVCC level due to an off-state current or the like of the fifthtransistor 35. However, the fifth transistor 35 of the pulse outputcircuit of this embodiment is a transistor having an extremely smalloff-state current, in which the first electrode layer is used as a maingate electrode. Therefore, the potential of the node B in the floatingstate is maintained stably and a reduction from the VCC level is small.Accordingly, a malfunction of the semiconductor device is suppressed andreliability is increased.

In addition, there is no need to employ a multi-gate structure such as adouble-gate structure or a triple-gate structure for suppression of anoff-state current of a transistor; therefore, the transistor can beminiaturized. Further, a capacitor for maintaining the potential of thenode B is unnecessary or can be miniaturized. In this manner, the totalsize of the semiconductor device can be reduced by using a pulse outputcircuit including a miniaturized element or a shift register including aminiaturized pulse output circuit.

The transistor in which the first electrode layer is used as a main gateelectrode has not only an off-state current that is reduced to beextremely small but also a positive threshold voltage. In the pulseoutput circuit of this embodiment, the transistor in which the firstelectrode layer is used as a main gate electrode is employed as thesecond transistor 32. Thus, the potential of the node A can be increasedspeedily by the bootstrap operation without much loss. Therefore, amalfunction of the semiconductor device is suppressed and reliability isincreased.

In the pulse output circuit of this embodiment, transistors in each ofwhich the fourth electrode layer using a crystalline region of apurified oxide semiconductor layer is used as a main gate electrode areused as the third transistor 33, the sixth transistor 36, the tenthtransistor 40, and the eleventh transistor 41. The transistor in whichthe fourth electrode layer is used as a main gate electrode hasexcellent f characteristics and a high field-effect mobility. Therefore,switching operation of the third transistor 33, the sixth transistor 36,the tenth transistor 40, and the eleventh transistor 41 can be madefaster. In addition, the transistors can be miniaturized.

Thus, the semiconductor device can operate at high speed by using apulse output circuit including an element which operates at high speedor a shift register including a pulse output circuit which operates athigh speed.

In addition, the shift register described in this embodiment uses adriving method in which a pulse that is output from the m-th pulseoutput circuit overlaps with half (¼ period) of a pulse that is outputfrom the (m+1)-th pulse output circuit, as shown in FIG. 8A. This canmake the time of charging a wiring with electricity twice as long asthat in a driving method in which a pulse that is output from the m-thpulse output circuit does not overlap with a pulse that is output fromthe (m+1)-th pulse output circuit in a conventional shift register (seeFIG. 8B). In this way, by using a driving method in which a pulse thatis output from the m-th pulse output circuit overlaps with half (¼period) of a pulse that is output from the (m+1)-th pulse outputcircuit, a pulse output circuit which can withstand large load andoperate at a high frequency can be provided. In addition, an operatingcondition of a pulse output circuit can be improved.

Note that the shift register and the pulse output circuit described inthis embodiment can be combined with any structure of a shift registerand a pulse output circuit described in the other embodiments of thisspecification. This embodiment of the present invention can also beapplied to a semiconductor device. A semiconductor device in thisspecification means a device that can function by utilizingsemiconductor characteristics.

Embodiment 4

In this embodiment, an example of forming a driver circuit of an activematrix display device by combining the shift register described inEmbodiment 3 manufactured using transistors having the four-terminalstructure in which a pair of electrode layers which are provided onopposite sides from each other with respect to a channel formationregion of an oxide semiconductor layer, each with an insulating filmarranged therebetween, with a switching circuit using a transistor inwhich a purified oxide semiconductor layer is used will be described.First, an overview of the active matrix display device is described withreference to block diagrams, and then a signal line driver circuit and ascan line driver circuit utilizing the shift register, which areprovided for the display device, are described.

FIG. 9A illustrates an example of a block diagram of an active matrixdisplay device. A pixel portion 5301, a first scan line driver circuit5302, a second scan line driver circuit 5303, and a signal line drivercircuit 5304 are provided over a substrate 5300 in the display device.In the pixel portion 5301, a plurality of signal lines extended from thesignal line driver circuit 5304 is arranged and a plurality of scanlines extended from the first scan line driver circuit 5302 and thesecond scan line driver circuit 5303 is arranged. Note that in crossregions of the scan lines and the signal lines, pixels each having adisplay element are arranged in a matrix. The substrate 5300 of thedisplay device is connected to a timing control circuit 5305 (alsoreferred to as a controller or a control IC) through a connectionportion such as a flexible printed circuit (FPC).

As a transistor disposed in the pixel portion 5301, a transistor of anembodiment described in Embodiment 1 can be employed. A transistor inwhich a first electrode layer provided in a side where a substrate isformed with a first insulating layer located therebetween is used as amain gate electrode is preferably used in the pixel portion 5301. Sincea transistor in which the first electrode layer is used as a mainelectrode has a small off-state current, contrast of a display image canbe increased and further power consumption of the display device can bereduced.

Since the transistors described in Embodiments 1 are n-channeltransistors, some of driver circuits that can be constituted byn-channel transistors among the driver circuits are formed over thesubstrate where the transistor of the pixel portion is formed.

In FIG. 9A, the first scan line driver circuit 5302, the second scanline driver circuit 5303, and the signal line driver circuit 5304 areformed over the substrate 5300 where the pixel portion 5301 is formed.Consequently, the number of components of a driver circuit and the likethat are provided outside the display device is reduced, so that costcan be reduced. Further, if the driver circuit is provided outside thesubstrate 5300, wirings need to be extended and the number ofconnections of wirings is increased. However, by providing the drivercircuit over the substrate 5300, the number of connections of thewirings can be reduced. Accordingly, an improvement in reliability or anincrease in yield can be achieved.

Note that the timing control circuit 5305 supplies, for example, a firstscan line driver circuit start signal (GSP1) and a scan line drivercircuit clock signal (GCK1) to the first scan line driver circuit 5302.Furthermore, the timing control circuit 5305 supplies, for example, asecond scan line driver circuit start signal (GSP2) (which is alsoreferred to as a start pulse) and a scan line driver circuit clocksignal (GCK2) to the second scan line driver circuit 5303. Moreover, thetiming control circuit 5305 supplies a signal line driver circuit startsignal (SSP), a signal line driver circuit clock signal (SCK), videosignal data (DATA, also simply referred to as a video signal), and alatch signal (LAT) to the signal line driver circuit 5304. Each clocksignal may be a plurality of clock signals with shifted phases or may besupplied together with a signal (CKB) obtained by inverting the clocksignal. Note that it is possible to omit one of the first scan linedriver circuit 5302 and the second scan line driver circuit 5303.

FIG. 9B illustrates a structure in which circuits with relatively lowdriving frequency (e.g., the first scan line driver circuit 5302 and thesecond scan line driver circuit 5303) are formed over the substrate 5300where the pixel portion 5301 is formed, and the signal line drivercircuit 5304 with relatively high driving frequency is formed over asubstrate which is different from the substrate 5300 where the pixelportion 5301 is formed. For example, the signal line driver circuit 5304with relatively high driving frequency can be formed over a differentsubstrate with the use of a transistor in which a single crystalsemiconductor is used. Thus, increase in size of the display device,reduction in the number of steps, reduction in cost, improvement inyield, or the like can be achieved.

In this embodiment, the signal line driver circuit 5304 with relativelyhigh driving frequency is formed over the same substrate 5300 as thepixel portion 5301. By providing the driver circuit over the substrate5300, the number of connections of wirings can be reduced. Accordingly,an improvement in reliability or an increase in yield can be achieved.

Next, an example of a structure and operation of a signal line drivercircuit constituted by n-channel transistors will be described withreference to FIGS. 10A and 10B.

The signal line driver circuit includes a shift register 5601 and aswitching circuit 5602. The switching circuit 5602 includes a pluralityof switching circuits 5602_1 to 5602_N (N is a natural number). Theswitching circuits 5602_1 to 5602_N each include a plurality oftransistors 5603_1 to 5603_k (k is a natural number). In thisembodiment, a structure in which the transistors 5603_1 to 5603_k aren-channel transistors is described below.

A connection relation in the signal line driver circuit is describedusing the switching circuit 5602_1 as an example with reference to FIG.10A. First terminals of the transistors 5603_1 to 5603_k are connectedto wirings 5604_1 to 5604_k, respectively. Second terminals of thetransistors 5603_1 to 5603_k are connected to signal lines S1 to Sk,respectively. Gates of the transistors 5603_1 to 5603_k are connected toa wiring 5605_1.

The shift register 5601 has a function of sequentially selecting theswitching circuits 5602_1 to 5602_N by sequentially outputting H-levelsignals (also referred to as H signals or signals at high power supplypotential levels) to wirings 5605_1 to 5605_N. The shift register 5601can be manufactured using the method described in Embodiment 3 anddetailed description thereof is omitted here.

The switching circuit 5602_1 has a function of controlling electricalcontinuity between the wirings 5604_1 to 5604_k and the signal lines S1to Sk (electrical continuity between the first terminals and the secondterminals), that is, a function of controlling whether potentials of thewirings 5604_1 to 5604_k are supplied to the signal lines S1 to Sk. Inthis manner, the switching circuit 5602_1 functions as a selector.Moreover, the transistors 5603_1 to 5603_k have functions of controllingelectrical continuity between the wirings 5604_1 to 5604_k and thesignal lines S1 to Sk, respectively, that is, functions of supplyingpotentials of the wirings 5604_1 to 5604_k to the signal lines S1 to Sk,respectively. In this manner, each of the transistors 5603_1 to 5603_kfunctions as a switch.

In this embodiment, transistors in which a crystalline region of apurified oxide semiconductor layer is used for a channel formationregion are used as transistors in the switching circuit 5602. Thetransistor in which a fourth electrode layer is used as a main gateelectrode has excellent dynamic characteristics and fast switchingoperation. Accordingly, the transistor can be used for high-speedwriting which is required in a next-generation high-definition displaydevice including many pixels. Note that since the transistor in which apurified oxide semiconductor layer is used for a channel formationregion can be manufactured using the method described in Embodiment 1,detailed description thereof is omitted here.

The video signal data (DATA) is input to each of the wirings 5604_1 to5604_k. The video signal data (DATA) is often an analog signal thatcorresponds to an image signal or image data.

Next, the operation of the signal line driver circuit in FIG. 10A isdescribed with reference to a timing chart in FIG. 10B. FIG. 10Billustrates examples of signals Sout_1 to Sout_N and signals Vdata_1 toVdata_k. The signals Sout_1 to Sout_N are examples of output signalsfrom the shift register 5601. The signals Vdata_1 to Vdata_k areexamples of signals input to the wirings 5604_1 to 5604_k. Note that oneoperation period of the signal line driver circuit corresponds to onegate selection period in a display device. For example, one gateselection period is divided into periods T1 to TN. Each of the periodsT1 to TN is a period for writing the video signal data (DATA) into apixel in a selected row.

Note that signal waveform distortion and the like in each structureillustrated in drawings and the like in this embodiment are exaggeratedfor simplicity in some cases. Therefore, this embodiment is notnecessarily limited to the scale illustrated in the drawings and thelike.

In the periods T1 to TN, the shift register 5601 sequentially outputsH-level signals to the wirings 5605_1 to 5605_N. For example, in theperiod T1, the shift register 5601 outputs an H-level signal to thewiring 5605_1. Then, the transistors 5603_1 to 5603_k are turned on, sothat the wirings 5604_1 to 5604_k and the signal lines S1 to Sk arebrought into conduction. At this time, Data(S1) to Data(Sk) are input tothe wirings 5604_1 to 5604_k, respectively. The Data(S1) to Data(Sk) arewritten into pixels in a first to kth columns in the selected rowthrough the transistors 5603_1 to 5603_k, respectively. In such amanner, in the periods T1 to TN, the video signal data (DATA) aresequentially written into the pixels in the selected row by k columns.

The video signal data (DATA) are written into pixels by a plurality ofcolumns as described above, whereby the number of video signal data(DATA) or the number of wirings can be reduced. Consequently, the numberof connections with an external circuit can be reduced. Moreover, thetime for writing can be extended when a video signal is written intopixels by a plurality of columns; thus, insufficient writing of a videosignal can be prevented.

The shift register described in Embodiment 3 is employed as the shiftregister 5601 of the driver circuit in this embodiment; therefore, amalfunction is suppressed and the shift register has high reliability.By using a miniaturized shift register, the total size of the drivercircuit can be reduced.

In addition, since transistors in which a crystalline region of apurified oxide semiconductor layer is used for a channel formationregion are used in the switching circuit 5602 of the driver circuit inthis embodiment, switching operation is fast. Accordingly, the drivercircuit exemplified in this embodiment can perform high speed writing topixels and is favorably used in a next-generation high-definitiondisplay device including many pixels.

The shift register described in Embodiment 3 can be applied to a scanline driver circuit as well. The scan line driver circuit includes ashift register. Additionally, the scan line driver circuit may include alevel shifter, a buffer, or the like in some cases. In the scan linedriver circuit, a clock signal (CLK) and a start pulse signal (SP) areinput to the shift register, so that a selection signal is generated.The selection signal generated is buffered and amplified by the buffer,and the resulting signal is supplied to a corresponding scan line. Gateelectrodes of transistors in pixels of one line are connected to thescan line. Since the transistors in the pixels of one line have to beturned on at the same time, a buffer that can supply large current isused.

The active matrix display device described in this embodiment isconnected to an external device through a terminal portion. A protectivecircuit is provided in the driver circuit in order to prevent generationof problems such as the shift in threshold value of the transistor whichis caused by abnormal input (e.g., static electricity) from the outside.Since the transistor in which the first electrode layer is used as amain electrode have a high withstand voltage between the gate and thesource and between the gate and the drain, they can be favorably used astransistors used in the protective circuit.

Embodiment 5

In this embodiment, an example of a structure of a terminal portionprovided over the same substrate as the transistors will be describedwith reference to FIGS. 22A1 to 22B2. Note that in FIGS. 22A1 to 22B2,components common to those of FIGS. 1A to 1E maintain the same referencenumerals.

FIGS. 22A1 and 22A2 respectively illustrate a cross-sectional view and atop view of the terminal portion of the gate wiring. FIG. 22A1 is thecross-sectional view taken along line C1-C2 of FIG. 22A2. In FIG. 22A1,a conductive layer 415 formed over the second insulating layer 428 is aterminal electrode for connection which functions as an input terminal.Furthermore, in a terminal portion of FIG. 22A1, a first terminal 411formed using the same material as the gate wiring and a connectionelectrode 412 formed using the same material as the source wiringoverlap each other with the first insulating layer 402 interposedtherebetween, and are in direct contact with each other so as to beelectrically connected to each other. In addition, the connectionelectrode 412 and the conductive layer 415 are directly connected toeach other through a contact hole formed in the second insulating layer428 so as to be electrically connected to each other.

FIGS. 22B1 and 22B2 respectively illustrate a cross-sectional view and atop view of a source wiring terminal portion. FIG. 22B1 is thecross-sectional view taken along line C3-C4 of FIG. 22B2. In FIG. 22B1,a conductive layer 418 formed over the second insulating layer 428 is aterminal electrode for connection which functions as an input terminal.Further in a terminal portion of FIG. 22B1, an electrode layer 416formed using the same material as the gate wiring is located below thesecond terminal 414 so as to overlapped with a second terminal 414electrically connected to the source wiring with the first insulatinglayer 402 interposed therebetween. The electrode layer 416 is notelectrically connected to the second terminal 414, and a capacitor forpreventing noise or static electricity can be formed if the potential ofthe electrode layer 416 is set to a potential different from that of thesecond terminal 414, such as floating, GND, or 0 V. The second terminal414 is electrically connected to the conductive layer 418, and thesecond insulating layer 428 is provided therebetween.

A plurality of gate wirings, source wirings, common potential lines, andpower supply lines is provided depending on the pixel density. In theterminal portion, a plurality of first terminals at the same potentialas the gate wiring, a plurality of second terminals at the samepotential as the source wiring, a plurality of third terminals at thesame potential as the power supply line, a plurality of fourth terminalsat the same potential as the common potential line, and the like arearranged. There is no particular limitation on the number of each of theterminals, and the number of such terminals may be determined by apractitioner as appropriate.

This embodiment can be freely combined with any of the otherembodiments.

Embodiment 6

By manufacturing transistors described in Embodiment 1 and using thetransistors for a pixel portion and driver circuits, a semiconductordevice having a display function (also referred to as a display device)can be manufactured. Moreover, some or all of the driver circuits whichinclude the transistors described in Embodiment 1 can be formed over asubstrate where the pixel portion is formed, whereby a system-on-panelcan be obtained.

The display device includes a display element. As the display element, aliquid crystal element (also referred to as a liquid crystal displayelement) or a light-emitting element (also referred to as alight-emitting display element) can be used. The light-emitting elementincludes, in its category, an element whose luminance is controlled by acurrent or a voltage, and specifically includes, in its category, aninorganic electroluminescent (EL) element, an organic EL element, andthe like. Furthermore, the display device may include a display mediumwhose contrast is changed by an electric effect, such as electronic ink.

In addition, the display device includes a panel in which the displayelement is sealed, and a module in which an IC and the like including acontroller are mounted on the panel. Furthermore, an element substrate,which is one embodiment before the display element is completed in amanufacturing process of the display device, is provided with a meansfor supplying current to the display element in each of a plurality ofpixels. Specifically, the element substrate may be in a state in whichonly a pixel electrode of the display element is formed, a state inwhich a conductive film to be a pixel electrode is formed but is notetched yet to form the pixel electrode, or any of the other states.

Note that a display device in this specification refers to an imagedisplay device, a display device, or a light source (including alighting device). Further, the display device also includes any of thefollowing modules in its category: a module to which a connector such asa flexible printed circuit (FPC), a tape automated bonding (TAB) tape,or a tape carrier package (TCP) is attached; a module having a TAB tapeor a TCP at the end of which a printed wiring board is provided; and amodule having an integrated circuit (IC) that is directly mounted on adisplay element by a chip on glass (COG) method.

In this embodiment, the appearance and a cross section of a liquidcrystal display panel, which is one embodiment of a semiconductordevice, will be described with reference to FIGS. 11A1, 11A2, and 11B.FIGS. 11A1 and 11A2 are plan views of panels, in which highly reliabletransistors 4010 and 4011 each including an In—Ga—Zn—O-based film as anoxide semiconductor layer described in Embodiment 1 and a liquid crystalelement 4013 are sealed between a first substrate 4001 and a secondsubstrate 4006 with a sealant 4005. FIG. 11B is a cross-sectional viewtaken along M-N in FIGS. 11A1 and 11A2.

The sealant 4005 is provided so as to surround a pixel portion 4002 anda scan line driver circuit 4004 which are provided over the firstsubstrate 4001. The second substrate 4006 is provided over the pixelportion 4002 and the scan line driver circuit 4004. Consequently, thepixel portion 4002 and the scan line driver circuit 4004 are sealedtogether with a liquid crystal layer 4008, by the first substrate 4001,the sealant 4005, and the second substrate 4006. A signal line drivercircuit 4003 that is formed using a single crystal semiconductor film ora polycrystalline semiconductor film over a substrate separatelyprepared is mounted in a region that is different from the regionsurrounded by the sealant 4005 over the first substrate 4001.

Note that there is no particular limitation on the connection method ofthe driver circuit which is separately formed, and a COG method, a wirebonding method, a TAB method, or the like can be used. FIG. 11A1illustrates an example in which the signal line driver circuit 4003 ismounted by a COG method. FIG. 11A2 illustrates an example in which thesignal line driver circuit 4003 is mounted by a TAB method.

The pixel portion 4002 and the scan line driver circuit 4004 providedover the first substrate 4001 include a plurality of transistors. FIG.11B illustrates the transistor 4010 included in the pixel portion 4002and the transistor 4011 included in the scan line driver circuit 4004,as an example. Insulating layers 4020 and 4041 are provided over thetransistor 4010, and an insulating layer 4021 is provided over thetransistor 4011. The insulating layer 4020 functions as a gateinsulating layer of the transistor 4011.

As the transistors 4010 and 4011, highly reliable transistors describedin Embodiment 1, each of which includes an In—Ga—Zn—O-based film as anoxide semiconductor layer, can be employed. In this embodiment, thetransistors 4010 and 4011 are n-channel transistors.

A pixel electrode layer 4030 included in the liquid crystal element 4013is electrically connected to the transistor 4010. A counter electrodelayer 4031 of the liquid crystal element 4013 is formed on the secondsubstrate 4006. A portion where the pixel electrode layer 4030, thecounter electrode layer 4031, and the liquid crystal layer 4008 overlapwith one another corresponds to the liquid crystal element 4013. Notethat the pixel electrode layer 4030 and the counter electrode layer 4031are provided with an insulating layer 4032 and an insulating layer 4033functioning as alignment films, respectively, and the liquid crystallayer 4008 is provided between the electrode layers with the insulatinglayers 4032 and 4033 arranged therebetween. Although not illustrated, acolor filter may be provided either on the first substrate 4001 side oron the second substrate 4006 side.

Note that the first substrate 4001 and the second substrate 4006 can beformed of glass, metal (typically, stainless steel), ceramics, orplastics. As plastics, a fiberglass-reinforced plastics (FRP) plate, apolyvinyl fluoride (PVF) film, a polyester film, or an acrylic resinfilm can be used. Alternatively, a sheet having a structure in which analuminum foil is arranged between PVF films or polyester films can beused.

A spacer 4035 is a columnar spacer obtained by selective etching of aninsulating film and provided in order to control the distance (a cellgap) between the pixel electrode layer 4030 and the counter electrodelayer 4031. Alternatively, a spherical spacer may be used. The counterelectrode layer 4031 is electrically connected to a common potentialline formed over the substrate where the transistor 4010 is formed. Thecounter electrode layer 4031 and the common potential line can beelectrically connected to each other through conductive particlesprovided between the pair of substrates using the common connectionportion. Note that the conductive particles are included in the sealant4005.

Alternatively, liquid crystal exhibiting a blue phase for which analignment film is unnecessary may be used. A blue phase is one of liquidcrystal phases, which is generated just before a cholesteric phasechanges into an isotropic phase while the temperature of cholestericliquid crystal is increased. Since the blue phase is only generatedwithin a narrow range of temperature, a liquid crystal compositioncontaining a chiral agent at 5 wt % or more is used for the liquidcrystal layer 4008 in order to improve the temperature range. The liquidcrystal composition including liquid crystal exhibiting a blue phase anda chiral agent has a short response time of 10 μsec to 100 μsecinclusive and is optically isotropic; therefore, alignment treatment isnot necessary and viewing angle dependence is small.

Note that although a transmissive liquid crystal display device isdescribed as an example in this embodiment, the present invention canalso be applied to either a reflective liquid crystal display device ora transflective liquid crystal display device.

Although a polarizing plate is provided on the outer surface of thesubstrate (on the viewer side) and a coloring layer and an electrodelayer used for a display element are sequentially provided on the innersurface of the substrate in the liquid crystal display device of thisembodiment, the polarizing plate may be provided on the inner surface ofthe substrate. The stacked structure of the polarizing plate and thecoloring layer is not limited to that in this embodiment and may be setas appropriate depending on materials of the polarizing plate and thecoloring layer or conditions of the manufacturing process. Further, alight-blocking film functioning as a black matrix may be provided.

In this embodiment, in order to reduce the surface roughness due to thetransistor and to improve the reliability of the transistor, thetransistors obtained in Embodiment 1 are covered with insulating layers(the insulating layers 4020 and 4021) functioning as a protective filmor a planarization insulating film. Note that the protective film isprovided to prevent entry of contaminant impurities such as an organicsubstance, metal, and moisture existing in the air and is preferably adense film. The protective film may be formed by a sputtering method tohave a single-layer structure or a stacked structure including any of asilicon oxide film, a silicon nitride film, a silicon oxynitride film, asilicon nitride oxide film, an aluminum oxide film, an aluminum nitridefilm, an aluminum oxynitride film, and an aluminum nitride oxide film.Although an example in which the protective film is formed by asputtering method is described in this embodiment, a variety of methodsmay be employed without limitation to the sputtering method.

In this embodiment, the insulating layer 4020 having a stacked structureis formed as a protective film. Here, a silicon oxide film is formedusing a sputtering method as a first layer of the insulating layer 4020.The use of the silicon oxide film as the protective film has an effectof preventing a hillock of an aluminum film which is used as the sourceand drain electrode layers.

As a second layer of the protective film, an insulating layer is formed.Here, a silicon nitride film is formed using a sputtering method, as thesecond layer of the insulating layer 4020. The use of the siliconnitride film as the protective film can prevent mobile ions of sodium orthe like from entering a semiconductor region, so that variation inelectric characteristics of the transistor can be suppressed.

After the protective film is formed, annealing (at higher than or equalto 300° C. and lower than or equal to 400° C.) of the oxidesemiconductor layers may be performed.

The insulating layer 4021 is formed as a planarization insulating film.The insulating layer 4021 can be formed using a heat-resistant organicmaterial such as an acrylic resin, polyimide, a benzocyclobutene-basedresin, polyamide, or an epoxy resin. Other than such organic materials,it is also possible to use a low-dielectric constant material (a low-kmaterial), a siloxane-based resin, phosphosilicate glass (PSG),borophosphosilicate glass (BPSG), or the like. Note that the insulatinglayer 4021 may be formed by stacking a plurality of insulating filmsformed using any of these materials.

Note that the siloxane-based resin corresponds to a resin including aSi—O—Si bond formed using a siloxane-based material as a startingmaterial. The siloxane-based resin may include as a substituent anorganic group (e.g., an alkyl group or an aryl group) or a fluoro group.In addition, the organic group may include a fluoro group.

The formation method of the insulating layer 4021 is not limited to aparticular method, and the following method can be used depending on thematerial: a sputtering method, an SOG method, a spin coating method, adipping method, a spray coating method, a droplet discharge method (suchas an inkjet method, screen printing, offset printing, or the like), orthe like. Further, the planarization insulating layer 4021 can be formedwith a doctor knife, a roll coater, a curtain coater, a knife coater, orthe like. In the case of forming the insulating layer 4021 with the useof a liquid material, annealing (at higher than or equal to 300° C. andlower than or equal to 400° C.) of the oxide semiconductor layers may beperformed at the same time as a baking step. When the baking step of theinsulating layer 4021 and the annealing of the oxide semiconductorlayers are combined, a semiconductor device can be manufacturedefficiently.

The pixel electrode layer 4030 and the counter electrode layer 4031 canbe formed using a light-transmitting conductive material such as indiumoxide containing tungsten oxide, indium zinc oxide containing tungstenoxide, indium oxide containing titanium oxide, indium tin oxidecontaining titanium oxide, indium tin oxide (hereinafter, referred to asITO), indium zinc oxide, or indium tin oxide to which silicon oxide isadded.

Alternatively, a conductive composition including a conductive highmolecule (also referred to as a conductive polymer) can be used for thepixel electrode layer 4030 and the counter electrode layer 4031. Thepixel electrode formed using the conductive composition preferably has asheet resistance of 10000 ohms per square or less and a lighttransmittance of 70% or more at a wavelength of 550 nm. Further, theresistivity of the conductive high molecule included in the conductivecomposition is preferably 0.1 Ω·cm or less.

As the conductive high molecule, a so-called π-electron conjugatedconductive polymer can be used. Examples are polyaniline and aderivative thereof, polypyrrole and a derivative thereof, polythiopheneand a derivative thereof, and a copolymer of two or more of thesematerials.

Further, a variety of signals and potentials are supplied to the signalline driver circuit 4003 which is separately formed and the scan linedriver circuit 4004 or the pixel portion 4002 from an FPC 4018.

In this embodiment, a connection terminal electrode 4015 is formed usingthe same conductive film as the pixel electrode layer 4030 included inthe liquid crystal element 4013. A terminal electrode 4016 is formedusing the same conductive film as source and drain electrode layers ofthe transistors 4010 and 4011.

The connection terminal electrode 4015 is electrically connected to aterminal included in the FPC 4018 via an anisotropic conductive film4019.

Note that FIGS. 11A1, 11A2, and 11B illustrate the example in which thesignal line driver circuit 4003 is formed separately and mounted on thefirst substrate 4001; however, this embodiment is not limited to thisstructure. The scan line driver circuit may be separately formed andthen mounted, or only part of the signal line driver circuit or part ofthe scan line driver circuit may be separately formed and then mounted.

FIG. 12 illustrates an example of a liquid crystal display module whichis formed as a semiconductor device using a transistor substrate 2600 towhich the transistors described in Embodiment 1 are applied.

FIG. 12 illustrates an example of the liquid crystal display module, inwhich the transistor substrate 2600 and a counter substrate 2601 arebonded to each other with a sealant 2602, and a pixel portion 2603including a transistor and the like, a display element 2604 including aliquid crystal layer, a coloring layer 2605, and the like are providedbetween the substrates to form a display region. The coloring layer 2605is necessary to perform color display. In the RGB system, coloringlayers corresponding to colors of red, green, and blue are provided forrespective pixels. Polarizing plates 2606 and 2607 and a diffusion plate2613 are provided outside the transistor substrate 2600 and the countersubstrate 2601. A light source includes a cold cathode tube 2610 and areflective plate 2611. A circuit board 2612 is connected to a wiringcircuit portion 2608 of the transistor substrate 2600 by a flexiblewiring board 2609 and includes an external circuit such as a controlcircuit or a power source circuit. The polarizing plate and the liquidcrystal layer may be stacked with a retardation plate interposedtherebetween.

For the liquid crystal display module, a twisted nematic (TN) mode, anin-plane-switching (IPS) mode, a fringe field switching (FFS) mode, amulti-domain vertical alignment (MVA) mode, a patterned verticalalignment (PVA) mode, an axially symmetric aligned micro-cell (ASM)mode, an optically compensated birefringence (OCB) mode, a ferroelectricliquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC)mode, or the like can be employed.

Through the above process, a highly reliable liquid crystal displaypanel as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combinedwith any of the structures described in the other embodiments asappropriate.

Embodiment 7

In this embodiment, an example of electronic paper is described as asemiconductor device to which the transistors described in Embodiment 1are applied.

FIG. 13 illustrates active matrix electronic paper as an example of asemiconductor device. The transistor described in Embodiment 1 can beused as a transistor 581 used for the semiconductor device. Thetransistor described in Embodiments 1 can be used as a transistor 581used for the semiconductor device.

The electronic paper in FIG. 13 is an example of a display device usinga twisting ball display system. The twisting ball display system refersto a method in which spherical particles each colored in black and whiteare arranged between a first electrode layer and a second electrodelayer which are electrode layers used for a display element, and apotential difference is generated between the first electrode layer andthe second electrode layer to control orientation of the sphericalparticles, so that display is performed.

The transistor 581 sealed between a substrate 580 and a substrate 596 isa transistor which is one embodiment of the present invention, and asource electrode layer and a drain electrode layer thereof is in contactwith a first electrode layer 587 at an opening formed in insulatinglayers 583 and 585, whereby the transistor 581 is electrically connectedto the first electrode layer 587. Between the first electrode layer 587and a second electrode layer 588, spherical particles 589 each having ablack region 590 a, a white region 590 b, and a cavity 594 around theregions, which is filled with liquid, are provided. A space around thespherical particles 589 is filled with a filler 595 such as a resin (seeFIG. 13). The cavity 594 in the spherical particle 589 is filled withliquid, and also includes a particle having the black region 590 a andthe white region 590 b. In this embodiment, the first electrode layer587 and the second electrode layer 588 correspond to a pixel electrodeand a common electrode, respectively. The second electrode layer 588 iselectrically connected to a common potential line provided over the samesubstrate as the transistor 581. With the use of any one of the commonconnection portions described in Embodiment 1, the second electrodelayer 588 and the common potential line can be electrically connected toeach other through conductive particles provided between the pair ofsubstrates.

Further, instead of the twisting ball, an electrophoretic element may beused. A microcapsule having a diameter approximately more than or equalto 10 μm and less than or equal to 200 μm in which transparent liquid,positively charged white microparticles, and negatively charged blackmicroparticles are encapsulated, is used. In the microcapsule which isprovided between the first electrode layer and the second electrodelayer, when an electric field is applied by the first electrode layerand the second electrode layer, the white microparticles and blackmicroparticles move to opposite sides from each other, so that white orblack can be displayed. A display element using this principle is anelectrophoretic display element and is generally called electronicpaper. The electrophoretic display element has a higher reflectivitythan a liquid crystal display element and thus, an auxiliary light isunnecessary, power consumption is low, and a display portion can berecognized in a dim place. In addition, even when power is not suppliedto the display portion, an image which has been displayed once can bemaintained. Accordingly, a displayed image can be stored even if asemiconductor device having a display function (which may be referred toas a display device simply or a semiconductor device provided with adisplay device) is distanced from a radio wave source.

Through the above process, highly reliable electronic paper as asemiconductor device can be manufactured.

Note that the structure described in this embodiment can be combinedwith any of the structures described in the other embodiments asappropriate.

Embodiment 8

In this embodiment, an example of a light-emitting display device willbe described as a semiconductor device to which the transistorsdescribed in Embodiment 1 are applied. A light-emitting elementutilizing electroluminescence will be described here as a displayelement included in the display device. Light-emitting elementsutilizing electroluminescence are classified according to whether alight-emitting material is an organic compound or an inorganic compound.In general, the former is referred to as an organic EL element, and thelatter is referred to as an inorganic EL element.

In an organic EL element, by application of voltage to a light-emittingelement, electrons and holes are separately injected from a pair ofelectrodes into a layer containing a light-emitting organic compound,and current flows. Then, the carriers (electrons and holes) recombine,so that the light-emitting organic compound is excited. Then, lightemission is caused when the light-emitting organic compound returns to aground state from the excited state. Owing to such a mechanism, thislight-emitting element is referred to as a current-excitationlight-emitting element.

The inorganic EL elements are classified according to their elementstructures into a dispersion-type inorganic EL element and a thin-filminorganic EL element. A dispersion-type inorganic EL element has alight-emitting layer where particles of a light-emitting material aredispersed in a binder, and its light emission mechanism isdonor-acceptor recombination type light emission which utilizes a donorlevel and an acceptor level. A thin-film inorganic EL element has astructure where a light-emitting layer is arranged between dielectriclayers, which are further arranged between electrodes, and its lightemission mechanism is localized type light emission that utilizesinner-shell electron transition of metal ions. Note that description ismade in this embodiment using an organic EL element as a light-emittingelement.

FIG. 14 illustrates an example of a pixel configuration to which digitaltime grayscale driving can be applied as an example of the semiconductordevice to which the present invention is applied. Note that the term“OS” in the drawing indicates a thin film transistor in which an oxidesemiconductor is used.

The configuration and operation of a pixel to which digital timegrayscale driving can be applied will be described. An example isdescribed here in which one pixel includes two n-channel transistorsdescribed in Embodiment 1, in each of which an oxide semiconductor layer(an In—Ga—Zn—O-based film) is used for a channel formation region.

A pixel 6400 includes a switching transistor 6401, a driving transistor6402, a light-emitting element 6404, and a capacitor 6403. In theswitching transistor 6401, a gate thereof is connected to a scan line6406, a first electrode thereof (one of source and drain electrodes) isconnected to a signal line 6405, and a second electrode thereof (theother of the source and drain electrodes) is connected to a gate of thedriving transistor 6402. In the driving transistor 6402, the gatethereof is connected to a power supply line 6407 through the capacitor6403, a first electrode thereof is connected to the power supply line6407, and a second electrode thereof is connected to a first electrode(pixel electrode) of the light-emitting element 6404. A second electrodeof the light-emitting element 6404 corresponds to a common electrode6408. The common electrode 6408 is electrically connected to a commonpotential line provided over the same substrate, and the connectionportion may be used as a common connection portion.

Note that the second electrode (common electrode 6408) of thelight-emitting element 6404 is set to a low power supply potential. Notethat the low power supply potential is a potential satisfying the lowpower supply potential<a high power supply potential with reference tothe high power supply potential that is set on the power supply line6407. As the low power supply potential, GND, 0 V, or the like may beemployed, for example. The difference between the high power supplypotential and the low power supply potential is applied to thelight-emitting element 6404 so that current flows through thelight-emitting element 6404, whereby the light-emitting element 6404emits light. Thus, each potential is set so that the difference betweenthe high power supply potential and the low power supply potential isgreater than or equal to a forward threshold voltage of thelight-emitting element 6404.

When the gate capacitance of the driving transistor 6402 is used as asubstitute for the capacitor 6403, the capacitor 6403 can be omitted.The gate capacitance of the driving transistor 6402 may be formedbetween the channel region and the gate electrode.

In the case of using a voltage-input voltage driving method, a videosignal is input to the gate of the driving transistor 6402 so that thedriving transistor 6402 is in either of two states of being sufficientlyturned on and turned off. That is, the driving transistor 6402 operatesin a linear region. A voltage higher than the voltage of the powersupply line 6407 is applied to the gate of the driving transistor 6402so that the driving transistor 6402 operates in a linear region. Notethat a voltage higher than or equal to the following is applied to thesignal line 6405: power supply line voltage+V_(th) of the drivingtransistor 6402.

In the case of performing analog grayscale driving instead of digitaltime grayscale driving, the same pixel configuration as FIG. 14 can beemployed by changing signal input.

In the case of performing analog grayscale driving, voltage higher thanor equal to the following is applied to the gate of the drivingtransistor 6402: forward voltage of the light-emitting element6404+V_(th) of the driving transistor 6402. The forward voltage of thelight-emitting element 6404 refers to voltage to obtain a desiredluminance, and includes at least forward threshold voltage. By input ofa video signal which enables the driving transistor 6402 to operate in asaturation region, it is possible to feed current to the light-emittingelement 6404. In order that the driving transistor 6402 can operate inthe saturation region, the potential of the power supply line 6407 isset higher than a gate potential of the driving transistor 6402. When ananalog video signal is used, it is possible to feed current to thelight-emitting element 6404 in accordance with the video signal andperform analog grayscale driving.

Note that the pixel configuration is not limited to that illustrated inFIG. 14. For example, the pixel illustrated in FIG. 14 may furtherinclude a switch, a resistor, a capacitor, a transistor, a logiccircuit, or the like.

Next, structures of the light-emitting element will be described withreference to FIGS. 15A to 15C. A cross-sectional structure of a pixelwill be described by taking an n-channel driving transistor as anexample. A transistor 7011, a transistor 7021, and a transistor 7001which are driving transistors used for semiconductor devices illustratedin FIGS. 15A, 15B, and 15C, respectively, can be manufactured in amanner similar to that of the transistor described in Embodiment 1, andare highly reliable transistors each including an In—Ga—Zn—O-based filmas an oxide semiconductor layer.

In order to extract light emitted from the light-emitting element, atleast one of the anode and the cathode is required to transmit light. Atransistor and a light-emitting element are formed over a substrate. Alight-emitting element can have a top emission structure in which lightis extracted through the surface opposite to the substrate, a bottomemission structure in which light is extracted through the surface onthe substrate side, or a dual emission structure in which light isextracted through the surface opposite to the substrate and the surfaceon the substrate side. The pixel configuration of the present inventioncan be applied to a light-emitting element having any of these emissionstructures.

A light-emitting element having a bottom emission structure will bedescribed with reference to FIG. 15A.

FIG. 15A is a cross-sectional view of a pixel in the case where thedriving transistor 7011 is of an n-type and light is emitted from alight-emitting element 7012 to a first electrode 7013 side. In FIG. 15A,the first electrode 7013 of the light-emitting element 7012 is formedover a conductive film 7017 having a light-transmitting property withrespect to visible light which is electrically connected to a drainelectrode layer of the driving transistor 7011, and an EL layer 7014 anda second electrode 7015 are stacked in that order over the firstelectrode 7013.

As the conductive film 7017 having a light-transmitting property withrespect to visible light, a conductive film having a light-transmittingproperty with respect to visible light such as a film of indium oxidecontaining tungsten oxide, indium zinc oxide containing tungsten oxide,indium oxide containing titanium oxide, indium tin oxide containingtitanium oxide, indium tin oxide, indium zinc oxide, or indium tin oxideto which silicon oxide is added can be used.

The first electrode 7013 of the light-emitting element can be formedusing various materials. For example, in the case where the firstelectrode 7013 is used as a cathode, a material having a low workfunction, for example, an alkali metal such as Li or Cs, analkaline-earth metal such as Mg, Ca, or Sr, an alloy containing any ofthese (Mg:Ag, Al:Li, or the like), a rare-earth metal such as Yb or Er,or the like, is preferably used. In FIG. 15A, the thickness of the firstelectrode 7013 is such that the first electrode transmits light(preferably, approximately 5 nm to 30 nm). For example, an aluminum filmhaving a thickness of 20 nm is used for the first electrode 7013.

Note that the conductive film having a light-transmitting property withrespect to visible light and the aluminum film may be stacked and thenselectively etched, so that the conductive film 7017 having alight-transmitting property with respect to visible light and the firstelectrode 7013 may be formed. In this case, the etching can be performedusing the same mask, which is preferable.

A partition 7019 is formed in the protective insulating layer 7035 andthe insulating layer 7032 and over a contact hole which reaches thedrain electrode layer, provided the conductive film 7017 therebetween.The peripheral portion of the first electrode 7013 may be covered with apartition. The partition 7019 is formed using an organic resin film suchas polyimide, an acrylic resin, polyamide, or an epoxy resin, aninorganic insulating film, or organic polysiloxane. It is particularlypreferable that the partition 7019 be formed using a photosensitiveresin material to have an opening over the first electrode 7013 so thata sidewall of the opening is formed as an inclined surface withcontinuous curvature. In the case where a photosensitive resin materialis used for the partition 7019, a step of forming a resist mask can beomitted.

The EL layer 7014 formed over the first electrode 7013 and the partition7019 may be formed using a single layer or a plurality of layers stackedas long as it includes at least a light-emitting layer. When the ELlayer 7014 is formed using a plurality of layers, the EL layer 7014 isformed by stacking an electron-injection layer, an electron-transportlayer, a light-emitting layer, a hole-transport layer, and ahole-injection layer in that order over the first electrode 7013functioning as a cathode. Note that not all of these layers need to beprovided.

The stacking order is not limited to the above stacking order. The firstelectrode 7013 may function as an anode, and a hole-injection layer, ahole-transport layer, a light-emitting layer, an electron-transportlayer, and an electron-injection layer may be stacked in that order overthe first electrode 7013. However, when power consumption is compared,it is preferable that the first electrode 7013 function as a cathode andan electron-injection layer, an electron-transport layer, alight-emitting layer, a hole-transport layer, and a hole-injection layerbe stacked in that order over the first electrode 7013, because anincrease in voltage in the driver circuit portion can be suppressed andpower consumption can be reduced.

As the second electrode 7015 formed over the EL layer 7014, variousmaterials can be employed. For example, in the case where the secondelectrode 7015 is used as an anode, a material having a high workfunction (specifically, a work function higher than or equal to 4.0 eV),such as ZrN, Ti, W, Ni, Pt, or Cr; or a light-transmitting conductivematerial such as ITO, IZO, or ZnO is preferably used. A light-blockingfilm 7016 is formed over the second electrode 7015 using, for example, ametal which blocks light, a metal which reflects light, or the like. Inthis embodiment, an ITO film is used for the second electrode 7015, anda Ti film is used for the light-blocking film 7016.

The light-emitting element 7012 corresponds to a region where the ELlayer 7014 including a light-transmitting layer is provided between thefirst electrode 7013 and the second electrode 7015. In the case of theelement structure illustrated in FIG. 15A, light is emitted from thelight-emitting element 7012 to the first electrode 7013 side asindicated by an arrow.

Note that in FIG. 15A, light emitted from the light-emitting element7012 passes through a color filter layer 7033, an insulating layer 7032,an oxide insulating layer 7031, a gate insulating layer 7030, and asubstrate 7010 and then is emitted.

The color filter layer 7033 is formed by a droplet discharge method suchas an ink-jet method, a printing method, an etching method with the useof a photolithography technique, or the like.

The color filter layer 7033 is covered with an overcoat layer 7034, andalso covered with a protective insulating layer 7035. Note that theovercoat layer 7034 having a thin thickness is illustrated in FIG. 15A;however, the overcoat layer 7034 is formed using a resin material suchas an acrylic resin and has a function of planarizing a surface havingunevenness due to the color filter layer 7033.

Next, a light-emitting element having a dual emission structure will bedescribed with reference to FIG. 15B.

In FIG. 15B, a first electrode 7023 of a light-emitting element 7022 isformed over a conductive film 7027 having a light-transmitting propertywith respect to visible light which is electrically connected to a drainelectrode layer of the driving transistor 7021, and an EL layer 7024 anda second electrode 7025 are stacked in that order over the firstelectrode 7023.

For the conductive film 7027 having a light-transmitting property withrespect to visible light, a conductive film having a light-transmittingproperty with respect to visible light of indium oxide containingtungsten oxide, indium zinc oxide containing tungsten oxide, indiumoxide containing titanium oxide, indium tin oxide containing titaniumoxide, indium tin oxide, indium zinc oxide, indium tin oxide to whichsilicon oxide is added, or the like can be used.

The first electrode 7023 can be formed using various materials. Forexample, in the case where the first electrode 7023 is used as acathode, a material having a low work function (specifically, less thanor equal to 3.8 eV), an alkali metal such as Li or Cs; an alkaline-earthmetal such as Mg, Ca, or Sr; an alloy containing any of these (Mg:Ag,Al:Li, or the like); a rare-earth metal such as Yb or Er; or the like ispreferable. In this embodiment, the first electrode 7023 is used as acathode and the first electrode 7023 is formed to a thickness such thatthe first electrode 7023 can transmit visible light (preferably,approximately 5 nm to 30 nm). For example, a 20-nm-thick aluminum filmis used as the cathode.

Note that the conductive film having a light-transmitting property withrespect to visible light and the aluminum film may be stacked and thenselectively etched, so that the conductive film 7027 having alight-transmitting property with respect to visible light and the firstelectrode 7023 may be formed. In that case, etching can be performedwith the use of the same mask, which is preferable.

A partition 7029 is formed in the protective insulating layer 7045 andthe insulating layer 7042 and over a contact hole which reaches thedrain electrode layer, provided the conductive film 7027 therebetween.The periphery of the first electrode 7023 may be covered with apartition. The partition 7029 is formed using an organic resin film suchas polyimide, an acrylic resin, polyamide, or an epoxy resin; aninorganic insulating film; or organic polysiloxane. It is particularlypreferable that the partition 7029 be formed using a photosensitiveresin material to have an opening over the first electrode 7023 so thata sidewall of the opening is formed as an inclined surface withcontinuous curvature. In the case where a photosensitive resin materialis used for the partition 7029, a step of forming a resist mask can beomitted.

The EL layer 7024 formed over the first electrode 7023 and the partition7029 may be formed using either a single layer or a plurality of layersstacked as long as it includes at least a light-emitting layer. When theEL layer 7024 is formed using a plurality of layers, the EL layer 7024is formed by stacking an electron-injection layer, an electron-transportlayer, a light-emitting layer, a hole-transport layer, and ahole-injection layer in that order over the first electrode 7023functioning as a cathode. Note that not all of these layers need to beprovided.

The stacking order is not limited to the above. The first electrode 7023may be used as an anode, and a hole-injection layer, a hole-transportlayer, a light-emitting layer, an electron-transport layer, and anelectron-injection layer may be stacked in that order over the anode.However, for lower power consumption, it is preferable that the firstelectrode 7023 be used as a cathode and an electron-injection layer, anelectron-transport layer, a light-emitting layer, a hole-transportlayer, and a hole-injection layer be stacked in this order over thecathode.

In addition, the second electrode 7025 formed over the EL layer 7024 canbe formed using a variety of materials. For example, when the secondelectrode 7025 is used as an anode, a material with a high work functionor a transparent conductive material such as ITO, IZO, or ZnO ispreferable. In this embodiment, the second electrode 7025 is formedusing an ITO film including silicon oxide and is used as an anode.

The light-emitting element 7022 corresponds to a region where the ELlayer 7024 including a light-emitting layer is provided between thefirst electrode 7023 and the second electrode 7025. In the case of theelement structure illustrated in FIG. 15B, light emitted from thelight-emitting element 7022 is emitted to both the second electrode 7025side and the first electrode 7023 side as indicated by arrows.

Note that in FIG. 15B, light emitted from the light-emitting element7022 to the first electrode 7023 side passes through a color filterlayer 7043, an insulating layer 7042, an oxide insulating layer 7041, agate insulating layer 7040, and a substrate 7020 and then is emitted.

The color filter layer 7043 is formed by a droplet discharge method suchas an ink-jet method, a printing method, an etching method with the useof a photolithography technique, or the like.

The color filter layer 7043 is covered with an overcoat layer 7044, andalso covered with a protective insulating layer 7045.

Note that when a light-emitting element having a dual emission structureis used and full color display is performed on both display surfaces,light from the second electrode 7025 side does not pass through thecolor filter layer 7043; therefore, a sealing substrate provided withanother color filter layer is preferably provided over the secondelectrode 7025.

Next, a light-emitting element having a top emission structure isdescribed with reference to FIG. 15C.

FIG. 15C is a cross-sectional view of a pixel in the case where thetransistor 7001, which is a driving transistor, is of n-type and lightis emitted from a light-emitting element 7002 to a second electrode 7005side. In FIG. 15C, a first electrode 7003 of the light-emitting element7002 is formed to be electrically connected to the drain electrode layerof the driving transistor 7001, and an EL layer 7004 and the secondelectrode 7005 are stacked in that order over the first electrode 7003.

The first electrode 7003 can be formed using a variety of materials. Forexample, in the case where the first electrode 7003 is used as acathode, a material having a low work function, for example, an alkalimetal such as Li or Cs, an alkaline-earth metal such as Mg, Ca, or Sr,an alloy containing any of these (Mg:Ag, Al:Li, or the like), arare-earth metal such as Yb or Er, or the like, is preferably used.

A partition 7009 is formed in the protective insulating layer 7052 andthe insulating layer 7055 and over a contact hole which reaches thedrain electrode layer, provided the conductive film 7003 therebetween.The periphery of the first electrode 7003 may be covered with apartition. The partition 7009 is formed using an organic resin film suchas polyimide, an acrylic resin, polyamide, or an epoxy resin; aninorganic insulating film; or organic polysiloxane. It is particularlypreferable that the partition 7009 be formed using a photosensitiveresin material to have an opening over the first electrode 7003 so thata sidewall of the opening is inclined with continuous curvature. Whenthe partition 7009 is formed using a photosensitive resin material, astep of forming a resist mask can be omitted.

The EL layer 7004 formed over the first electrode 7003 and the partition7009 may be formed using either a single layer or a plurality of layersstacked as long as it includes at least a light-emitting layer. When theEL layer 7004 is formed using a plurality of layers, the EL layer 7004is formed by stacking an electron-injection layer, an electron-transportlayer, a light-emitting layer, a hole-transport layer, and ahole-injection layer in that order over the first electrode 7003 used asa cathode. Note that not all of these layers need to be provided.

The stacking order is not limited to the above stacking order, and ahole-injection layer, a hole-transport layer, a light-emitting layer, anelectron-transport layer, and an electron-injection layer may be stackedin that order over the first electrode 7003 used as an anode.

In FIG. 15C, a hole-injection layer, a hole-transport layer, alight-emitting layer, an electron-transport layer, and anelectron-injection layer are stacked in that order over a stacked filmin which a Ti film, an aluminum film, and a Ti film are stacked in thatorder, and thereover, a stacked layer of a Mg:Ag alloy thin film and ITOis formed.

However, in the case where the transistor 7001 is of an n-type, it ispreferable that an electron-injection layer, an electron-transportlayer, a light-emitting layer, a hole-transport layer, and ahole-injection layer be stacked in that order over the first electrode7003, because an increase in voltage in the driver circuit can besuppressed and power consumption can be reduced.

The second electrode 7005 is formed using a conductive material having alight-transmitting property with respect to visible light, and forexample, a conductive film having a light-transmitting property withrespect to visible light of indium oxide containing tungsten oxide,indium zinc oxide containing tungsten oxide, indium oxide containingtitanium oxide, indium tin oxide containing titanium oxide, indium tinoxide, indium zinc oxide, indium tin oxide to which silicon oxide isadded, or the like can be used.

The light-emitting element 7002 corresponds to a region where the ELlayer 7004 is provided between the first electrode 7003 and the secondelectrode 7005. In the case of the pixel illustrated in FIG. 15C, lightis emitted from the light-emitting element 7002 to the second electrode7005 side as indicated by an arrow.

In FIG. 15C, the drain electrode layer of the transistor 7001 iselectrically connected to the first electrode 7003 through a contacthole provided in an oxide insulating layer 7051, a protective insulatinglayer 7052, and an insulating layer 7055. A planarizing insulating layer7053 can be formed using a resin material such as polyimide, an acrylicresin, benzocyclobutene, polyamide, or an epoxy resin. In addition tosuch resin materials, it is also possible to use a low-dielectricconstant material (low-k material), a siloxane-based resin,phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or thelike. Note that the planarization insulating layer 7053 may be formed bystacking a plurality of insulating films formed of these materials.There is no particular limitation on the method for forming theplanarization insulating layer 7053, and the planarization insulatinglayer 7053 can be formed, depending on the material, using a method suchas a sputtering method, an SOG method, spin coating, dip coating, spraycoating, or a droplet discharge method (such as an inkjet method, screenprinting, offset printing, or the like), or a tool (equipment) such as adoctor knife, a roll coater, a curtain coater, or a knife coater.

In the structure of FIG. 15C, when full color display is performed, forexample, the light-emitting element 7002 is used as a greenlight-emitting element, one of adjacent light-emitting elements is usedas a red light-emitting element, and the other is used as a bluelight-emitting element. Alternatively, a light-emitting display devicecapable of full color display may be manufactured using four kinds oflight-emitting elements, which include white light-emitting elements inaddition to three kinds of light-emitting elements.

In the structure of FIG. 15C, a light-emitting display device capable offull color display may be manufactured in such a way that all of aplurality of light-emitting elements which is arranged is whitelight-emitting elements and a sealing substrate having a color filter orthe like is arranged on the light-emitting element 7002. A materialwhich exhibits light of a single color such as white can be formed andcombined with a color filter or a color conversion layer, whereby fullcolor display can be performed.

Needless to say, display of monochromatic light can also be performed.For example, a lighting device may be formed with the use of white lightemission, or an area-color light-emitting device may be formed with theuse of a single color light emission.

If necessary, an optical film such as a polarizing film including acircularly polarizing plate may be provided.

Although an organic EL element is described here as a light-emittingelement, an inorganic EL element can also be provided as alight-emitting element.

Note that the example is described in which a transistor which controlsthe driving of a light-emitting element (a driving transistor) iselectrically connected to the light-emitting element; however, astructure may be employed in which a transistor for current control isconnected between the driving transistor and the light-emitting element.

A semiconductor device described in this embodiment is not limited tothe structures illustrated in FIGS. 15A to 15C and can be modified invarious ways based on the technical spirit of the present invention.

Next, the appearance and a cross section of a light-emitting displaypanel (also referred to as a light-emitting panel) which is anembodiment of a semiconductor device to which the transistors describedin Embodiment 1 are applied will be described with reference to FIGS.16A and 16B. FIG. 16A is a plan view of a panel in which a transistorand a light-emitting element are sealed between a first substrate and asecond substrate with a sealant. FIG. 16B is a cross-sectional viewtaken along line H-I of FIG. 16A.

A sealant 4505 is provided to surround a pixel portion 4502, a signalline driver circuit 4503 a, a signal line driver circuit 4503 b, a scanline driver circuit 4504 a, and a scan line driver circuit 4504 b, whichare provided over a first substrate 4501. In addition, a secondsubstrate 4506 is provided over the pixel portion 4502, the signal linedriver circuits 4503 a and 4503 b, and the scan line driver circuits4504 a and 4504 b. Accordingly, the pixel portion 4502, the signal linedriver circuits 4503 a and 4503 b, and the scan line driver circuits4504 a and 4504 b are sealed together with a filler 4507, by the firstsubstrate 4501, the sealant 4505, and the second substrate 4506. It ispreferable that a display device be thus packaged (sealed) with aprotective film (such as a bonding film or an ultraviolet curable resinfilm) or a cover material with high air-tightness and littledegasification so that the display device is not exposed to the outsideair.

The pixel portion 4502, the signal line driver circuits 4503 a and 4503b, and the scan line driver circuits 4504 a and 4504 b formed over thefirst substrate 4501 each include a plurality of transistors, and atransistor 4510 included in the pixel portion 4502 and a transistor 4509included in the signal line driver circuit 4503 a are illustrated as anexample in FIG. 16B.

For each of the transistors 4509 and 4510, the highly reliabletransistor described in Embodiment 1 which includes an In—Ga—Zn—O-basedfilm as an oxide semiconductor layer can be applied. In this embodiment,the transistors 4509 and 4510 are n-channel transistors.

A conductive layer 4540 is provided over an insulating layer 4544 in aportion which overlaps with the channel formation region of the oxidesemiconductor layer of the transistor 4509 for the driver circuit. Whenthe conductive layer 4540 is provided in a portion which overlaps withthe channel formation region of the oxide semiconductor layer, theamount of shift in the threshold voltage of the transistor 4509 betweenbefore and after a BT test can be reduced. The conductive layer 4540 mayhave a potential which is the same as or different from that of the gateelectrode layer of the transistor 4509, and can function as a secondgate electrode layer. The potential of the conductive layer 4540 may beGND, 0 V or in a floating state.

Reference numeral 4511 denotes a light-emitting element, and a firstelectrode layer 4517 that is a pixel electrode included in thelight-emitting element 4511 is electrically connected to a sourceelectrode layer or a drain electrode layer of the transistor 4510. Notethat the structure of the light-emitting element 4511 is not limited tothe structure described in this embodiment, which includes the firstelectrode layer 4517, an electroluminescent layer 4512, and a secondelectrode layer 4513. The structure of the light-emitting element 4511can be changed as appropriate depending on the direction in which lightis extracted from the light-emitting element 4511, or the like.

A partition 4520 is formed using an organic resin film, an inorganicinsulating film, or organic polysiloxane. It is particularly preferablethat the partition 4520 be formed of a photosensitive material to havean opening over the first electrode layer 4517 so that a sidewall of theopening is formed as an inclined surface with continuous curvature.

The electroluminescent layer 4512 may be formed using a single layer ora plurality of layers stacked.

A protective film may be formed over the second electrode layer 4513 andthe partition 4520 in order to prevent oxygen, hydrogen, moisture,carbon dioxide, or the like from entering the light-emitting element4511. As the protective film, a silicon nitride film, a silicon nitrideoxide film, a DLC (diamond-like carbon) film, or the like can be formed.

In addition, a variety of signals and potentials are supplied to thesignal line driver circuits 4503 a and 4503 b, the scan line drivercircuits 4504 a and 4504 b, or the pixel portion 4502 from an FPC 4518 aand an FPC 4518 b.

In this embodiment, a connection terminal electrode 4515 is formed fromthe same conductive film as the first electrode layer 4517 included inthe light-emitting element 4511, and a terminal electrode 4516 is formedfrom the same conductive film as the source and drain electrode layersincluded in the transistors 4509 and 4510.

The connection terminal electrode 4515 is electrically connected to aterminal included in the FPC 4518 a through an anisotropic conductivefilm 4519.

The substrate located in the direction in which light is extracted fromthe light-emitting element 4511 needs to have a light-transmittingproperty with respect to visible light. In that case, a material havinga light-transmitting property with respect to visible light such as aglass plate, a plastic plate, a polyester film, or an acrylic resin filmis used.

As the filler 4507, an ultraviolet curable resin or a thermosettingresin can be used, in addition to an inert gas such as nitrogen orargon. For example, PVC (polyvinyl chloride), an acrylic resin,polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), orEVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogenis used as the filler.

In addition, if needed, an optical film such as a polarizing plate, acircularly polarizing plate (including an elliptically polarizingplate), a retardation plate (a quarter-wave plate or a half-wave plate),or a color filter may be provided as appropriate on a light-emittingsurface of the light-emitting element. Further, the polarizing plate orthe circularly polarizing plate may be provided with an anti-reflectionfilm. For example, anti-glare treatment by which reflected light can bediffused by projections and depressions on the surface so as to reducethe glare can be performed.

The signal line driver circuits 4503 a and 4503 b and the scan linedriver circuits 4504 a and 4504 b may be mounted as driver circuitsformed using a single crystal semiconductor film or a polycrystallinesemiconductor film over a substrate separately prepared. Alternatively,only the signal line driver circuits or part thereof, or only the scanline driver circuits or part thereof may be separately formed andmounted. This embodiment is not limited to the structure illustrated inFIGS. 16A and 16B.

Through the above process, a highly reliable light-emitting displaydevice (display panel) as a semiconductor device can be manufactured.

Note that the structure described in this embodiment can be combinedwith any of the structures described in the other embodiments asappropriate.

Embodiment 9

A semiconductor device to which the transistors described in Embodiment1 are applied can be used as electronic paper. Electronic paper can beused for electronic devices of a variety of fields as long as they candisplay data. For example, electronic paper can be applied to anelectronic book reader (e-book), a poster, an advertisement in a vehiclesuch as a train, displays of various cards such as a credit card, andthe like.

Examples of the electronic devices are illustrated in FIGS. 17A and 17Band FIG. 18.

FIG. 17A illustrates a poster 2631 formed using electronic paper. In thecase where an advertising medium is printed paper, the advertisement isreplaced by manpower; however, by using electronic paper, theadvertising display can be changed in a short time. Further, an imagecan be stably displayed without display deterioration. Note that theposter may have a configuration capable of wirelessly transmitting andreceiving data.

FIG. 17B illustrates an advertisement 2632 in a vehicle such as a train.In the case where an advertising medium is printed paper, theadvertisement is replaced by manpower; however, by using electronicpaper, the advertising display can be changed in a short time without alot of manpower. Further an image can be stably displayed withoutdisplay deterioration. Note that the advertisement in a vehicle may havea configuration capable of wirelessly transmitting and receiving data.

FIG. 18 illustrates an example of an electronic book reader. Forexample, an electronic book reader 2700 includes two housings, a housing2701 and a housing 2703. The housing 2701 and the housing 2703 arecombined with a hinge 2711 so that the electronic book reader 2700 canbe opened and closed with the hinge 2711 as an axis. With such astructure, the electronic book reader 2700 can be operated like a paperbook.

A display portion 2705 and a display portion 2707 are incorporated inthe housing 2701 and the housing 2703, respectively. The display portion2705 and the display portion 2707 may display one image or differentimages. In the case where the display portion 2705 and the displayportion 2707 display different images, for example, a display portion onthe right side (the display portion 2705 in FIG. 18) can display textand a display portion on the left side (the display portion 2707 in FIG.18) can display graphics.

FIG. 18 illustrates an example in which the housing 2701 is providedwith an operation portion and the like. For example, the housing 2701 isprovided with a power switch 2721, an operation key 2723, a speaker2725, and the like. With the operation key 2723, pages can be turned.Note that a keyboard, a pointing device, and the like may be provided onthe same surface as the display portion of the housing. Further, anexternal connection terminal (an earphone terminal, a USB terminal, aterminal that can be connected to various cables such as an AC adapterand a USB cable, or the like), a recording medium insertion portion, andthe like may be provided on the back surface or the side surface of thehousing. Further, the electronic book reader 2700 may have a function ofan electronic dictionary.

The electronic book reader 2700 may have a configuration capable ofwirelessly transmitting and receiving data. A structure may be employedin which a desired book data or the like is purchased and downloadedfrom an electronic book server wirelessly.

Note that the structure described in this embodiment can be combinedwith any of the structures described in the other embodiments asappropriate.

Embodiment 10

The semiconductor device including the transistors described inEmbodiment 1 can be applied to a variety of electronic devices(including game machines). Examples of such electronic devices are atelevision device (also referred to as a television or a televisionreceiver), a monitor of a computer or the like, a camera such as adigital camera or a digital video camera, a digital photo frame, amobile phone (also referred to as a cellular phone or a mobile phonedevice), a portable game console, a portable information terminal, anaudio playback device, a large-sized game machine such as a pinballmachine, and the like.

FIG. 19A illustrates an example of a television device. In a televisiondevice 9600, a display portion 9603 is incorporated in a housing 9601.The display portion 9603 can display images. Here, the housing 9601 issupported by a stand 9605.

The television device 9600 can be operated with an operation switch ofthe housing 9601 or a separate remote controller 9610. Channels can beswitched and volume can be controlled with operation keys 9609 of theremote controller 9610, whereby an image displayed on the displayportion 9603 can be controlled. Moreover, the remote controller 9610 maybe provided with a display portion 9607 for displaying data output fromthe remote controller 9610.

Note that the television device 9600 is provided with a receiver, amodem, and the like. With the receiver, general TV broadcasts can bereceived. Moreover, when the display device is connected to acommunication network with or without wires via the modem, one-way (froma sender to a receiver) or two-way (e.g., between a sender and areceiver or between receivers) information communication can beperformed.

FIG. 19B illustrates an example of a digital photo frame. For example,in a digital photo frame 9700, a display portion 9703 is incorporated ina housing 9701. The display portion 9703 can display a variety ofimages. For example, the display portion 9703 can display image datataken with a digital camera or the like and function as a normal photoframe.

Note that the digital photo frame 9700 is provided with an operationportion, an external connection terminal (a USB terminal, a terminalconnectable to a variety of cables such as a USB cable), a recordingmedium insertion portion, and the like. Although these components may beprovided on the same surface as the display portion, it is preferable toprovide them on the side surface or the back surface for designaesthetics. For example, a memory that stores image data taken with adigital camera is inserted into the recording medium insertion portionof the digital photo frame 9700 and the data is loaded, whereby theimage can be displayed on the display portion 9703.

The digital photo frame 9700 may be configured to transmit and receivedata wirelessly. Through wireless communication, desired image data canbe loaded to be displayed.

FIG. 20A illustrates a portable game console including two housings, ahousing 9881 and a housing 9891 which are jointed with a joint portion9893 so that the portable game console can be opened or folded. Adisplay portion 9882 and a display portion 9883 are incorporated in thehousing 9881 and the housing 9891, respectively. In addition, theportable game console illustrated in FIG. 20A is provided with a speakerportion 9884, a recording medium insertion portion 9886, an LED lamp9890, input means (operation keys 9885, a connection terminal 9887, asensor 9888 (having a function of measuring force, displacement,position, speed, acceleration, angular velocity, rotation number,distance, light, liquid, magnetism, temperature, chemical substance,sound, time, hardness, electric field, current, voltage, electric power,radial ray, flow rate, humidity, gradient, vibration, smell, or infraredray), and a microphone 9889), and the like. Needless to say, thestructure of the portable game console is not limited to the above andanother structure which is provided with at least a semiconductor deviceaccording to the present invention can be employed. The portable gameconsole may include an additional accessory as appropriate. The portablegame console illustrated in FIG. 20A has a function of reading a programor data stored in a recording medium to display it on the displayportion, and a function of sharing data with another portable gameconsole via wireless communication. Note that a function of the portablegame console illustrated in FIG. 20A is not limited to those describedabove, and the portable game console can have a variety of functions.

FIG. 20B illustrates an example of a slot machine which is a large-sizedgame machine. In a slot machine 9900, a display portion 9903 isincorporated in a housing 9901. In addition, the slot machine 9900includes an operation means such as a start lever or a stop switch, acoin slot, a speaker, and the like. Needless to say, the structure ofthe slot machine 9900 is not limited to the above and another structurewhich is provided with at least the semiconductor device according tothe present invention may be employed. The slot machine 9900 may includean additional accessory as appropriate.

FIG. 21A illustrates an example of a mobile phone. A mobile phone 1000includes a housing 1001 in which a display portion 1002 is incorporated,an operation button 1003, an external connection port 1004, a speaker1005, a microphone 1006, and the like.

Information can be input to the mobile phone 1000 illustrated in FIG.21A by touching the display portion 1002 with a finger or the like.Moreover, users can make a call or write an e-mail by touching thedisplay portion 1002 with their fingers or the like.

There are mainly three screen modes of the display portion 1002. Thefirst mode is a display mode mainly for displaying images. The secondmode is an input mode mainly for inputting information such as text. Thethird mode is a display-and-input mode in which two modes of the displaymode and the input mode are combined.

For example, in the case of making a call or writing an e-mail, thedisplay portion 1002 may be placed into a text input mode mainly forinputting text, and characters displayed on a screen can be input. Inthis case, it is preferable to display a keyboard or number buttons onalmost the entire area of the screen of the display portion 1002.

When a detection device including a sensor which detects inclination,such as a gyroscope or an acceleration sensor, is provided inside themobile phone 1000, display on the screen of the display portion 1002 canbe automatically switched by detecting the direction of the mobile phone1000 (whether the mobile phone 1000 is placed horizontally or verticallyfor a landscape mode or a portrait mode).

Further, the screen modes are switched by touching the display portion1002 or operating the operation button 1003 of the housing 1001.Alternatively, the screen modes can be switched depending on the kindsof image displayed on the display portion 1002. For example, when asignal for an image displayed on the display portion is data of movingimages, the screen mode is switched to the display mode. When the signalis text data, the screen mode is switched to the input mode.

Further, in the input mode, a signal is detected by an optical sensor inthe display portion 1002 and if input by touching the display portion1002 is not performed for a certain period, the screen mode may becontrolled so as to be switched from the input mode to the display mode.

The display portion 1002 can also function as an image sensor. Forexample, an image of a palm print, a fingerprint, or the like is takenwhen the display portion 1002 is touched with the palm or the finger,whereby personal authentication can be performed. Moreover, when abacklight or sensing light source which emits near-infrared light isprovided in the display portion, an image of finger veins, palm veins,or the like can be taken.

FIG. 21B illustrates another example of a mobile phone. The mobile phonein FIG. 21B has a display device 9410 provided with a housing 9411including a display portion 9412 and operation buttons 9413, and acommunication device 9400 provided with a housing 9401 includingoperation buttons 9402, an external input terminal 9403, a microphone9404, a speaker 9405, and a light-emitting portion 9406 that emits lightwhen a phone call is received. The display device 9410 having a displayfunction can be detachably attached to the communication device 9400having a phone function in two directions represented by the arrows.Thus, the display device 9410 and the communication device 9400 can beattached to each other along their short sides or long sides. Inaddition, when only the display function is needed, the display device9410 can be detached from the communication device 9400 and used alone.Images or input information can be transmitted or received by wirelessor wire communication between the communication device 9400 and thedisplay device 9410, each of which has a rechargeable battery.

Note that the structure described in this embodiment can be combinedwith any of the structures described in the other embodiments asappropriate.

This application is based on Japanese Patent Application serial no.2009-255535 filed with Japan Patent Office on Nov. 6, 2009, the entirecontents of which are hereby incorporated by reference.

1. (canceled)
 2. A semiconductor device comprising: a first transistor;and a second transistor, wherein the first transistor comprises: a firstconductive film; a first oxide semiconductor layer over the firstconductive film; and a second conductive film over the first oxidesemiconductor layer, wherein the second transistor comprises: a thirdconductive film; a second oxide semiconductor layer over the thirdconductive film; and a fourth conductive film over the second oxidesemiconductor layer, wherein the first oxide semiconductor layercomprises In, Ga and Zn, wherein the second oxide semiconductor layercomprises In, Ga and Zn, wherein the first oxide semiconductor layercomprises a first crystal region on a surface of the first oxidesemiconductor layer, wherein the first oxide semiconductor layer has achannel formation region in the first crystal region, wherein the secondoxide semiconductor layer comprises a second crystal region on a surfaceof the second oxide semiconductor layer, wherein the second oxidesemiconductor layer has a channel formation region in the second crystalregion, wherein the first conductive film and the first oxidesemiconductor layer overlap each other, and have a region as a firstgate electrode, wherein the second conductive film and the first oxidesemiconductor layer overlap each other, and have a region as a secondgate electrode, wherein the third conductive film and the second oxidesemiconductor layer overlap each other, and have a region as a thirdgate electrode, wherein the fourth conductive film and the second oxidesemiconductor layer overlap each other, and have a region as a fourthgate electrode, wherein one of a source electrode and a drain electrodeof the first transistor is electrically connected to a first wiring,wherein the other of the source electrode and the drain electrode of thefirst transistor is electrically connected to one of a source electrodeand a drain electrode of the second transistor, and wherein the other ofthe source electrode and the second electrode is electrically connectedto a second wiring.
 3. The semiconductor device according to claim 2,wherein each of the first conductive film, the second conductive film,the third conductive film and the fourth conductive film has alight-transmitting property.
 4. The semiconductor device according toclaim 2, wherein each of the first crystal region and the second crystalregion comprises a nanocrystal.
 5. The semiconductor device according toclaim 3, wherein each of the first crystal region and the second crystalregion comprises a nanocrystal.